AD5726 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5726 Datasheet PDF : 20 Pages
| |||
AD5726
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AVDD 1
VOUTD 2
VOUTC 3
VREFN 4
VREFP 5
VOUTB 6
VOUTA 7
AVSS 8
AD5726
TOP VIEW
(Not to Scale)
16 CLRSEL
15 CLR
14 LDAC
13 NC
12 CS
11 SCLK
10 SDIN
9 GND
NC = NO CONNECT
Figure 5. 16-Lead SSOP and 16-Lead SOIC Pin Configuration
AVDD 1
VOUTD 2
VOUTC 3
VREFN 4
NC 5
NC 6
VREFP 7
VOUTB 8
VOUTA 9
AVSS 10
AD5726
TOP VIEW
(Not to Scale)
20 CLRSEL
19 CLR
18 LDAC
17 NC
16 NC
15 NC
14 CS
13 SCLK
12 SDIN
11 GND
NC = NO CONNECT
Figure 6. 20-Lead SSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
16-Lead SSOP/SOIC 20-Lead SSOP
1
1
2
2
3
3
4
4
5
7
6
8
7
9
8
10
9
11
10
12
11
13
12
14
13
5, 6, 15, 16, 17
14
18
15
19
16
20
Mnemonic
AVDD
VOUTD
VOUTC
VREFN
VREFP
VOUTB
VOUTA
AVSS
GND
SDIN
SCLK
CS
NC
LDAC
CLR
CLRSEL
Description
Positive Analog Supply Pin. Voltage range is from 5 V to 15 V.
Buffered Analog Output Voltage of DAC D.
Buffered Analog Output Voltage of DAC C.
Negative DAC Reference Input. The voltage applied to this pin defines the zero-scale
output. Allowable range is AVSS to VREFP − 2.5 V.
Positive DAC Reference Input. The voltage applied to this pin defines the full-scale
output voltage. Allowable range is AVDD − 2.5 V to VREFN + 2.5 V.
Buffered Analog Output Voltage of DAC B.
Buffered Analog Output Voltage of DAC A.
Negative Analog Supply Pin. Voltage range is from 0 V to −15 V.
Ground Reference Pin.
Serial Data Input. Data must bevalid on the rising edgeof SCLK. This input isignored
when CS is high.
Serial Clock Input. Data is clocked into the input register on the rising edge of SCLK.
Active Low Chip Select Pin. This pin must be active for data to be clocked in. This pin
is logically OR’ed with the SCLK input and disables the serial data input when high.
No Internal Connection.
Active Low, Asynchronous Load DAC Input. The data currently contained in the
serial input register is transferred out to the DAC data registers on the falling edge
of LDAC, independent of CS. Input data must remain stable while LDAC is low.
Active Low Input. Sets input register and DAC registers to zero-scale (0x000) or
midscale (0x800), depending on the state of CLRSEL. The data in the serial input
register is unaffected by this control.
Determines the action of CLR. If high, a clear command sets the internal DAC
registers to midscale (0x800). If low, the registers are set to zero (0x000).
Rev. C | Page 8 of 20
Share Link: 