AD5726(Rev0) Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5726 Datasheet PDF : 20 Pages
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AD5726
TIMING CHARACTERISTICS
AVDD = +15 V/+5 V, AVSS = −15 V/−5 V/0 V, GND = 0 V; VREFP = +10 V/+2.5 V; VREFN = −10 V/−2.5 V/0 V, VL = 5 V, RLOAD = 2 kΩ,
CL = 200 pF. All specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 5.
Parameter
tDS
tDH
tCH
tCL
tCSS
tCSH
tLD1
tLD2
tLDW
tCLRW
Limit at TMIN, TMAX
5
5
13
13
13
13
20
20
20
20
Unit
Description
ns
Data setup time.
ns
Data hold time.
ns
Clock pulse width high.
ns
Clock pulse width low.
ns
Select time.
ns
Deselect delay.
ns
Load disable time.
ns
Load delay.
ns
Load pulse width.
ns
Clear pulse width.
1 Guaranteed by design and characterization, not production tested.
2 All input control signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
CS
SDIN
tCSS
A1
A0
X
X
D11 D10
D9
D8
tCSH
D4
D3
D2
D1
D0
SCLK
LDAC
tLD1
tLD2
Figure 2. Data Load Sequence
SDIN
tDS
tDH
SCLK
tCL
CS
LDAC
VOUT
tCH
tCSH
tLD2
tLDW
tS
±1LSB
Figure 3. Data Load Timing
CLRSEL
CLR
VOUT
tCLRW
tS
±1LSB
Figure 4. Clear Timing
Rev. 0 | Page 6 of 20
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