AD7951(2015) Ver la hoja de datos (PDF) - Analog Devices
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AD7951 Datasheet PDF : 32 Pages
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Data Sheet
AD7951
TIMING SPECIFICATIONS
AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15 V; VEE = −15 V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (See Figure 33 and Figure 34)
Convert Pulse Width
Time Between Conversions
Warp Mode/Normal Mode/Impulse Mode1
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Warp Mode/Normal Mode/Impulse Mode
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Warp Mode/Normal Mode/Impulse Mode
Acquisition Time
Warp Mode/Normal Mode/Impulse Mode
RESET Pulse Width
PARALLEL INTERFACE MODES (See Figure 35 and Figure 37)
CNVST Low to DATA Valid Delay
Warp Mode/Normal Mode/Impulse Mode
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES2 (See Figure 39 and Figure 40)
CS Low to SYNC Valid Delay
CS Low to Internal SDCLK Valid Delay2
CS Low to SDOUT Delay
CNVST Low to SYNC Delay, Read During Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Asserted to SDCLK First Edge Delay
Internal SDCLK Period3
Internal SDCLK High3
Internal SDCLK Low3
SDOUT Valid Setup Time3
SDOUT Valid Hold Time3
SDCLK Last Edge to SYNC Delay3
CS High to SYNC High-Z
CS High to Internal SDCLK High-Z
CS High to SDOUT High-Z
BUSY High in Master Serial Read After Convert3
CNVST Low to SYNC Delay, Read After Convert
Warp Mode/Normal Mode/Impulse Mode
SYNC Deasserted to BUSY Low Delay
Symbol Min
Typ
Max
Unit
t1
10
t2
1/1.25/1.49
t3
t4
t5
2
t6
10
t7
t8
148
t9
10
ns
μs
35
ns
850/1100/1350 ns
ns
ns
850/1100/1350 ns
ns
ns
t10
t11
20
t12
t13
2
850/1100/1350 ns
ns
40
ns
15
ns
t14
10
ns
t15
10
ns
t16
10
ns
t17
50/290/530
ns
t18
3
ns
t19
30
45
ns
t20
15
ns
t21
10
ns
t22
4
ns
t23
5
ns
t24
5
ns
t25
10
ns
t26
10
ns
t27
10
ns
t28
See Table 4
t29
710/950/1190
ns
t30
25
ns
Rev. B | Page 5 of 32
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