AD5381(RevA) Ver la hoja de datos (PDF) - Analog Devices
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AD5381 Datasheet PDF : 36 Pages
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AD5381
I2C SERIAL INTERFACE TIMING
Table 7. DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
TMIN to TMAX, unless otherwise noted
Parameter1, 2
Limit at TMIN, TMAX
Unit
Description
FSCL
400
kHz max SCL clock frequency
t1
2.5
µs min
SCL cycle time
t2
0.6
µs min
tHIGH, SCL high time
t3
1.3
µs min
tLOW, SCL low time
t4
0.6
µs min
tHD,STA, start/repeated start condition hold time
t5
100
ns min
tSU,DAT, data setup time
t63
0.9
µs max
tHD,DAT, data hold time
0
µs min
tHD,DAT, data hold time
t7
0.6
µs min
tSU,STA, setup time for repeated start
t8
0.6
µs min
tSU,STO, stop condition setup time
t9
1.3
µs min
tBUF, bus free time between a STOP and a START condition
t10
300
ns max
tR, rise time of SCL and SDA when receiving
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
300
ns max
tF, fall time of SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
300
ns max
tF, fall time of SCL and SDA when receiving
20 + 0.1Cb 4
ns min
tF, fall time of SCL and SDA when transmitting
Cb
400
pF max
Capacitive load for each bus line
1 Guaranteed by design and characterization, not production tested.
2 See Figure 6.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) in order to bridge the undefined region of
SCL’s falling edge.
4 Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3DVDD and 0.7DVDD.
SDA
t9
t3
t10
t11
t4
SCL
t4
START
CONDITION
t6
t2
t5
t1
t7
REPEATED
START
CONDITION
Figure 6. I2C Compatible Serial Interface Timing Diagram
t8
STOP
CONDITION
Rev. A | Page 10 of 36
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