AD5372 Ver la hoja de datos (PDF) - Analog Devices
Número de pieza
componentes Descripción
Fabricante
AD5372 Datasheet PDF : 28 Pages
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AD5372/AD5373
TIMING CHARACTERISTICS
DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pF to GND;
RL = open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. SPI Interface
Parameter 1, 2, 3
Limit at TMIN, TMAX
t1
20
t2
8
t3
8
t4
11
t5
20
t6
10
t7
5
t8
5
t9 4
42
t10
1/1.5
t11
600
t12
20
t13
10
t14
3
t15
0
t16
3
t17
20/30
t18
140
t19
30
t20
400
t21
270
t22 5
25
t23
80
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs typ/μs max
ns max
ns min
ns min
μs max
ns min
μs max
μs typ/μs max
ns max
ns min
μs max
ns min
ns max
ns max
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low (single-channel update); see Table 9
Single-channel update cycle time
SYNC rising edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR/RESET pulse activation time
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
RESET rising edge to BUSY falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 4 and Figure 5.
4 t9 is measured with the load circuit shown in Figure 2.
5 t22 is measured with the load circuit shown in Figure 3.
TO
OUTPUT
PIN
DVCC
RL
2.2kΩ
VOL
CL
50pF
Figure 2. Load Circuit for BUSY Timing Diagram
200µA
IOL
TO OUTPUT
PIN CL
50pF
VOH (MIN) – VOL (MAX)
2
200µA
IOH
Figure 3. Load Circuit for SDO Timing Diagram
Rev. C | Page 6 of 28
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