AD8176-EVAL(2007) Ver la hoja de datos (PDF) - Analog Devices
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AD8176-EVAL Datasheet PDF : 32 Pages
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AD8176
Preliminary Technical Data
TIMING CHARACTERISTICS (PARALLEL MODE)
Table 7.
Parameter
Parallel Data Setup Time
WE Pulse Width
Parallel Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On or Off
WE, UPDATE Rise and Fall Times
RST Time
Specifications subject to change without notice.
t2
1
WE
0
t1
t3
1
D0 TO D4
A0 TO A4
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
Symbol
Min
t1
80
t2
110
t3
150
t4
90
t5
10
t6
90
t4
Figure 3. Timing Diagram, Parallel Mode
Limit
Typ
Max
TBD
TBD
TBD
t5
t6
Table 8. Logic Levels, VDD = 3.3 V
VIH
VIL
VOH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
SEROUT
2.0 V min
0.6 V max
Disabled
VOL
SEROUT
Disabled
IIH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
20 μA max
IIL
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
A3, UPDATE
−20 μA max
IOH
SEROUT
Disabled
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
IOL
SEROUT
Disabled
Table 9. H and V Logic Levels, VDD = 3.3 V
VOH
VOL
2.7 V min
0.5 V max
IOH
–3 mA max
IOL
3 mA max
Table 10. RST Logic Levels, VDD = 3.3 V
VIH
VIL
2.0 V min
0.6 V max
IIH
−60 μA max
IIL
−120 μA max
Table 11. CSB Logic Levels, VDD = 3.3 V
VOH
VOL
2.0 V min
0.6 V max
IIH
100 μA max
IOL
40 μA max
Rev. PrA | Page 6 of 32
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