AD9776ABSVZRL Ver la hoja de datos (PDF) - Analog Devices
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AD9776ABSVZRL Datasheet PDF : 56 Pages
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AD9776A/AD9778A/AD9779A
DIGITAL INPUT DATA TIMING SPECIFICATIONS
All modes, −40°C to +85°C.
Table 3.
Parameter
INPUT DATA1
Setup Time
Hold Time
Setup Time
Hold Time
LATENCY
1× Interpolation
2× Interpolation
4× Interpolation
8× Interpolation
Inverse Sync
3-WIRE INTERFACE
Maximum Clock Rate (SCLK)
Minimum Pulse Width High, tPWH
Minimum Pulse Width Low, tPWL
Setup Time, tDS
Hold Time, tDH
Setup Time, tDS
Data Valid, tDV
POWER-UP TIME2
RESET
Minimum Pulse Width, High
Conditions
Input data to DATACLK
Input data to DATACLK
Input data to REFCLK
Input data to REFCLK
With or without modulation
With or without modulation
With or without modulation
With or without modulation
SDIO to SCLK
SDIO to SCLK
CSB to SCLK
SDO to SCLK
Min
3.0
−0.05
−0.80
3.80
40
Typ
25
70
146
297
18
2.8
0.0
2.8
2.0
260
Max
12.5
12.5
2
Unit
ns
ns
ns
ns
DACCLK cycles
DACCLK cycles
DACCLK cycles
DACCLK cycles
DACCLK cycles
MHz
ns
ns
ns
ns
ns
ns
ms
DACCLK cycles
1 Specified values are with PLL disabled. Timing vs. temperature and data valid keep out windows (that is, the minimum amount of time valid data must be presented to
the device to ensure proper sampling) are delineated in Table 28.
2 Measured from CSB rising edge when Register 0x00, Bit 4, is written from 1 to 0 with the VREF decoupling capacitor equal to 0.1 μF.
Rev. B | Page 7 of 56
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