55LD019A-45-I-BWE Ver la hoja de datos (PDF) - Silicon Storage Technology
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55LD019A-45-I-BWE Datasheet PDF : 79 Pages
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ATA Flash Disk Controller
SST55LD019A / SST55LD019B / SST55LD019C
Data Sheet
TABLE 3-1: Pin Assignments (Continued) (2 of 4)
Symbol
WP_PD#
Pin No.
85-
100-TQFP VFBGA
62
D2
84-
TFBGA
F9
Pin
Type
I
I/O
Type1
I1U
Name and Functions
The WP_PD# pin can be used for either the Write Protect
mode or Power-down mode, but only one mode is active at any
time. The Write Protect or Power-down modes can be selected
through the host command. The Write Protect mode is the fac-
tory default setting.
Flash Media Interface
FWP#
97
H7
FRDYbsy#
82
J3
FRE#
84
H3
FWE#
96
J7
FCLE
92
K6
FALE
94
H6
FAD15
46
A3
FAD14
44
B4
FAD13
42
C5
FAD12
40
A5
FAD11
35
C7
FAD10
33
A7
FAD9
31
B8
FAD8
29
B9
FAD7
45
C4
FAD6
43
A4
FAD5
41
B5
FAD4
39
C6
FAD3
34
B7
FAD2
32
C8
FAD1
30
A8
FAD0
28
A9
FCE6#
91
H5
FCE5#
95
K7
FCE4#
93
J6
FCE3#
89
J5
FCE2#
88
H4
FCE1#
80
K3
FCE0#
86
J4
FCE7#/
26
C9
INTCLKEN
B4
O
O5 Active Low Flash Media Chip Write Protect
Connect this pin to the NAND flash media Write Protect pin
A8
I
I4U Flash Media Chip Ready/Busy#
Signal high is flash media ready signal. Low is busy.
B7
Active Low Flash Media Chip Read
A4
Active Low Flash Media Chip Write
O
O5
C6
Active High Flash Media Chip Command Latch Enable
B5
Active High Flash Media Chip Address Latch Enable
K8
K7
H6
J5
I/O I3U/O5 Flash Media Chip High Byte Address/Data Bus pins
H5
K3
J3
J2
J7
J6
K6
K5
I/O I3U/O5 Flash Media Chip Low Byte Address/Data Bus pins
J4
H4
K2
H3
B6
C5
A5
A6
O
O4 Active Low Flash Media Chip Enable pin
C7
B8
A7
J1
O I3D/O4 Active Low Flash Media Chip Enable pin
This pin is sensed during the Power-on Reset (POR) to select
an internal clock mode. If this pin is pulled up during the
Power-on Reset then the internal clock is selected.
©2006 Silicon Storage Technology, Inc.
11
S71241-04-000
12/06
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