AD9361 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9361

RF Agile Transceiver

Analog Devices 

AD9361

Parameter1

Logic Outputs

Output Voltage

High

Low

Output Differential Voltage

Output Offset Voltage

GENERAL-PURPOSE OUTPUTS

Output Voltage

High

Low

Output Current

SPI TIMING

SPI_CLK

Period

Pulse Width

SPI_ENB Setup to First SPI_CLK

Rising Edge

Last SPI_CLK Falling Edge to

SPI_ENB Hold

SPI_DI

Data Input Setup to SPI_CLK

Data Input Hold to SPI_CLK

SPI_CLK Rising Edge to Output

Data Delay

4-Wire Mode

3-Wire Mode

Bus Turnaround Time, Read

Bus Turnaround Time, Read

DIGITAL DATA TIMING (CMOS),

VDD_INTERFACE = 1.8 V

DATA_CLK Clock Period

DATA_CLK and FB_CLK Pulse

Width

TX Data

Setup to FB_CLK

Hold to FB_CLK

DATA_CLK to Data Bus Output

Delay

DATA_CLK to RX_FRAME Delay

Pulse Width

ENABLE

TXNRX

TXNRX Setup to ENABLE

Bus Turnaround Time

Before RX

After RX

Capacitive Load

Capacitive Input

Symbol Min

1025

150

VDD_GPO × 0.8

tCP

20

tMP

9

tSC

1

tHC

0

tS

2

tH

1

tCO

3

tCO

3

tHZM

tH

tHZS

0

tCP

16.276

tMP

45% of tCP

tSTX

1

tHTX

0

tDDRX

0

tDDDV

0

tENPW

tCP

tTXNRXPW tCP

tTXNRXSU 0

tRPRE

tRPST

2 × tCP

2 × tCP

Typ

1200

10

3

3

Data Sheet

Test Conditions/

Max

Unit

Comments

1375

mV

mV

mV

Programmable in 75 mV

steps

mV

VDD_GPO × 0.2

V

V

mA

VDD_INTERFACE = 1.8 V

ns

ns

ns

ns

ns

ns

8

8

tCO (max)

tCO (max)

ns

ns

ns

After BBP drives the last

address bit

ns

After AD9361 drives the

last data bit

55% of tCP

1.5

1.0

ns

61.44 MHz

ns

TX_FRAME, P0_D, and

P1_D

ns

ns

ns

ns

ns

ns

FDD independent ENSM

mode

ns

TDD ENSM mode

ns

TDD mode

ns

TDD mode

pF

pF

Rev. F | Page 6 of 36

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