AD9361 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Fabricante

AD9361

RF Agile Transceiver

Analog Devices 

Data Sheet

AD9361

Parameter1

TX MONITOR INPUTS (TX_MON1,

TX_MON2)

Maximum Input Level

Dynamic Range

Accuracy

LO SYNTHESIZER

LO Frequency Step

Integrated Phase Noise

800 MHz

2.4 GHz

5.5 GHz

REFERENCE CLOCK (REF_CLK)

Input

Frequency Range

Signal Level

AUXILIARY CONVERTERS

ADC

Resolution

Input Voltage

Minimum

Maximum

DAC

Resolution

Output Voltage

Minimum

Maximum

Output Current

DIGITAL SPECIFICATIONS (CMOS)

Logic Inputs

Input Voltage

High

Low

Input Current

High

Low

Logic Outputs

Output Voltage

High

Low

DIGITAL SPECIFICATIONS (LVDS)

Logic Inputs

Input Voltage Range

Input Differential Voltage

Threshold

Receiver Differential Input

Impedance

Symbol Min

Typ

Max

4

66

1

2.4

0.13

0.37

0.59

Unit

dBm

dB

dB

Hz

° rms

° rms

° rms

19

50

10

80

1.3

12

0.05

VDDA1P3_BB − 0.05

10

0.5

VDD_GPO − 0.3

10

MHz

MHz

V p-p

Bits

V

V

Bits

V

V

mA

VDD_INTERFACE × 0.8

0

−10

−10

VDD_INTERFACE

V

VDD_INTERFACE × 0.2 V

+10

μA

+10

μA

VDD_INTERFACE × 0.8

V

VDD_INTERFACE × 0.2 V

825

1575

mV

−100

+100

mV

100

Ω

Rev. F | Page 5 of 36

Test Conditions/

Comments

2.4 GHz, 40 MHz

reference clock

100 Hz to 100 MHz,

30.72 MHz reference clock

(doubled internally for RF

synthesizer)

100 Hz to 100 MHz,

40 MHz reference clock

100 Hz to 100 MHz,

40 MHz reference clock

(doubled internally for RF

synthesizer)

REF_CLK is either the input

to the XTALP/XTALN pins

or a line directly to the

XTALN pin

Crystal input

External oscillator

AC-coupled external

oscillator

Each differential input in

the pair

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