TY72011AP2G Ver la hoja de datos (PDF) - ON Semiconductor

Número de pieza

componentes Descripción

Fabricante

TY72011AP2G

Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback

ON Semiconductor 

TY72011AP2

Error Amplifier and Fault Detection

The TY72011 features an internal error amplifier solely

used to detect an overcurrent problem. The application

assumes that all the error gain associated with the precise

reference level is located on the secondary side of the SMPS.

Various solutions can be purposely implemented such as the

TL431 or a dedicated circuit like the MC33341. In the

TY72011, the internal OPAMP is used to create a virtual

ground permanently biased at 2.5 V (Figure 7), an internal

reference level. By monitoring this virtual ground further

called V(-), we have the possibility to confirm the good

behavior of the loop. If by any mean the loop is broken

(shorted optocoupler, open LED etc.) or the regulation

cannot be reached (true output short-circuit), the OPAMP

network is adjusted in order to no longer be able to ensure

the 2.5 V virtual point V(-). If V(-) passes down the 1.5 V

level (e.g. output shorted) for a time longer than 128 ms,

then the pulses are stopped for 8 x 128 ms. The IC enters a

kind of burst mode with bunch of pulses lasting 128 ms and

repeating every 8 x 128 ms. If the loop is restored within the

8 x 128 ms period, then the pulses are back again on the

output drive (synchronized with UVLOH).

Monitor

Rf

150 k

Vfb

Ri

50 k V(-)

+

Vfb

VHIGH = 3 V

VLOW = 5 mV

-

3+

1

2R

Current

2

6 Setpoint

+

R

V1

2.5 V

+

Vlow

1.5 V

+

-7

5

OCP

Circuitry

Figure 7.

To illustrate how the system reacts to a variable FB level,

we have entered the above circuit into a SPICE simulator

and observed the output waveforms. When FB is within

regulation, the error flag is low. However, as soon as FB

leaves its normal operating area, the OPAMP can no longer

keep the V(-) point and either goes to the positive top or

down to zero: the error flag goes high.

Because of the large amount of delay necessary for this

128 ms operation, the capacitor used for the timing is Ct,

connected from ground to pin 5. In normal VFM operation,

this timing capacitor serves as the VCO capacitor and the

error management circuit is transparent. As soon as an error

is detected (error flag goes high), an internal switch routes

Ct to the 128 ms generator. As a first effect, the switching

frequency is no longer controlled by the VCO (if the error

appears during VFM) and the system is relaxed to natural

BCM. The capacitor now ramps up and down to be further

divided and finally create the 128 ms delay.

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