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componentes Descripción

Fabricante

53C810

PCI-SCSI I/O Processor

Unspecified 

PRELIMINARY

Chapter One

Introduction

• Allows a multi-threaded I/O algorithm to be

executed in SCSI SCRIPTS with fast I/O

context switching

Allows relative jumps

Fetch, Master, and Memory Access control

pins.

• Allows indirect fetching of DMA address and

byte counts so that SCRIPTS can be placed

in a PROM

Separate SCSI and system clocks

• Voltage feed through protection (minimum

leakage current through SCSI pads)

• 25% of pins are power and ground

Power and ground isolation of I/O pads and

internal chip logic

NCR TolerANT technology provides:

• Active negation of SCSI Data, Parity,

Request, and Acknowledge signals for

improved fast SCSI transfer rates.

• Input signal filtering on SCSI receivers;

improves data integrity, even in noisy

cabling environments.

Reliability

• 2 K volts ESD protection on SCSI signals

Typical 350 mV SCSI bus hysteresis

Protection against bus reflections due to

impedance mismatches

Controlled bus assertion times (reduces RFI,

improves reliability, and eases FCC certifica-

tion)

• Latch-up protection greater than 150 rnA

Testability

• All SCSI signals accessible through pro-

grammedI/O

• SCSI loopback diagnostics

• SCSI bus signal continuity checking

• Supports single-step mode operation

• Test mode (AND tree) to check pin continuity

to the board

Figure 1-1. SCSI Port Logic

I SCSI Connection

Ii

SCSI Tenn Connection

PCI

NCR

Bus

53C810

1SCLK

40 MHz Oscillator or

Optional

Internal Connection

to PCI Bus Clock

CPU Baseboard

CPU Box

SCSI Bus

NCR 53C810 Data Manual

1-3

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