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TZA3026 Datasheet PDF : 15 Pages
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Philips Semiconductors
TZA3026
SDH/SONET STM4/OC12 transimpedance amplifier
The parasitic capacitance can be minimized through:
1. Reducing the capacitance of the PIN diode. This is achieved by proper choice of PIN
diode and typically a high reverse voltage.
2. Reducing the parasitics around the input pad. This is achieved by placing the PIN
diode as close as possible to the TIA.
The PIN diode can be biased with a positive or a negative voltage. Figure 3 shows the PIN
diode biased positively, using the on-chip bias pad DREF. The voltage at DREF is derived
from VCC by a low-pass filter comprising internal resistor RDREF and external capacitor C2
which decouples any supply voltage noise. The value of external capacitor C2 affects the
value of PSRR and should have a minimum value of 470 pF. Increasing this value
improves the value of PSRR. The current through RDREF is measured and sourced at pad
IDREF_MON, see Section 7.3.
If the biasing for the PIN diode is done external to the IC, pad DREF can be left
unconnected. If a negative bias voltage is used, the configuration shown in Figure 4 can
be used. In this configuration, the direction of the signal current is reversed to that shown
in Figure 3. It is essential that in these applications, the PIN diode bias voltage is filtered to
achieve the best sensitivity.
For maximum freedom on bonding location, 2 outputs are available for DREF (pads 1
and 3). These are internally connected. Both outputs can be used if necessary. If only one
is used, the other can be left open.
C2
470 pF
VCC
DREF 1 or 3 RDREF
IPD
300
4 or 17
IPHOTO 2
TZA3026
001aac619
Fig 3. The PIN diode connected between
the input and pad DREF
VCC
DREF 1 or 3 RDREF
300
4 or 17
IPHOTO 2
IPD
negative
bias voltage
TZA3026
001aac620
Fig 4. The PIN diode connected between
the input and a negative supply
voltage
9397 750 14763
Product data sheet
Rev. 01 — 2 May 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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