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SPCA711A Ver la hoja de datos (PDF) - Unspecified

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SPCA711A Datasheet PDF : 20 Pages
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SPCA711A
Mnemonic PIN No. Type
Description
SVIDEO
SLEEP
MODEA
MODEB
CLK
XTALO
TEST
VREFIN
VREFOUT
FSADJ
COMP
VBIAS
VDD
DGND
CVBSY
CVBSC
Cr and Cb sequence.
14
I SVIDEO select input pin. A logic high selects Y/C output. A logic low
selects composite video output.
13
I Power save mode. A logic high on this pin puts the chip into power-
down mode. This pin is equal to reset pin. An external logic high pulse
should input to the pin when power on.
17
I Mode configuration pin.
18
I Mode configuration pin.
19
I 27MHz crystal oscillator input. A crystal with 27MHz clock frequency can
be connected between this pin and XTALO.
20
O Crystal oscillator output.
2
I Test pin. These pins must be connected to DGND.
9
I Voltage reference input. An external voltage reference must supply
typical 1.235V to this pin. A 0.1µF ceramic capacitor must be used to
de-couple this input to GND. The decoupling capacitor must be as
closed as possible to minimize the length of the load. This pin may be
connected directly to VREFOUT.
8
O Voltage reference output. It generates typical 1.2V voltage reference
and may be used to drive VREFIN pin directly.
5
- Full-Scale adjust control pin. The Full-Scale current of D/A converters
can be adjusted by connecting a resistor (RSET) between this pin and
ground.
6
-
Compensation pin. A 0.1µF ceramic capacitor must be used to bypass
this pin to VAA. The lead length must be kept as short as possible to
avoid noise.
10
- DAC bias voltage. Potential normally 0.7V less than COMP.
31
- Digital power pin
30
- Digital ground pin
4
O Composite/Luminance output. This is a high-impedance current source
output. The output format can be selected by the PAL pin. The
CVBSY can drive a 37.5 load.
11
O Composite/Chroma output. This is a high impedance current source
Output. The output format can be selected by the PAL pin. The pin
can drive a 37.5 load.
                                                       

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