S25FL128P0XNFI011 Ver la hoja de datos (PDF) - Spansion Inc.
Número de pieza
componentes Descripción
Fabricante
S25FL128P0XNFI011
Spansion Inc.
S25FL128P0XNFI011 Datasheet PDF : 49 Pages
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Data Sheet
3. Input/Output Descriptions
Signal Name
SO (Signal Data Output)
PO[7–0] (Parallel Data Input/Output)
SI (Serial Data Input)
SCK (Serial Clock)
CS# (Chip Select)
HOLD# (Hold)
WP#/ACC
(Write Protect/Accelerated Programming)
VCC
GND
I/O
Output
Input/Output
Input
Input
Input
Input
Input
Input
Input
Description
Transfers data serially out of the device on the falling edge of SCK.
Transfers parallel data into the device on the rising edge of SCK or out of
the device on the falling edge of SCK.
Transfers data serially into the device. Device latches commands,
addresses, and program data on SI on the rising edge of SCK.
Provides serial interface timing. Latches commands, addresses, and data
on SI on rising edge of SCK. Triggers output on SO after the falling edge
of SCK.
Places device in active power mode when driven low. Deselects device
and places SO at high impedance when high. After power-up, device
requires a falling edge on CS# before any command is written. Device is
in standby mode when a program, erase, or Write Status Register
operation is not in progress.
Pauses any serial communication with the device without deselecting it.
When driven low, SO is at high impedance, and all input at SI and SCK
are ignored. Requires that CS# also be driven low.
When driven low, prevents any program or erase command from altering
the data in the protected memory area specified by Status Register bits
(BP bits). If the system asserts VHH on this pin, accelerated
programming operation is provided.
Supply Voltage
Ground
4. Logic Symbol
VCC
SI
SCK
CS#
WP#/ACC
HOLD#
GND
SO
PO[7-0] (For 16-pin SO package)
September 21, 2012 S25FL128P_00_11
S25FL128P
9
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