MSM5718B70-50GS-K Ver la hoja de datos (PDF) - Oki Electric Industry

Número de pieza

componentes Descripción

Fabricante

MSM5718B70-50GS-K

18-Megabit RDRAM (2M x 9)

Oki Electric Industry 

MSM5718B70

Signal

BusData [8-0]

RxClk

TxClk

Vref

BusCtrl

BusEnable

Vdd, VddA

Gnd, GndA

SIn

SOut

¡ Semiconductor

Table 2 Pin Descriptions

I/O

Description

Signal lines for request, write data, and read data packets. The request

packet contains the address, operation codes, and the count of the bytes

I/O

to be transferred. These are low-swing active-low signals referenced to

Vref.

I

Receive clock. Incoming request and write data packets are aligned to

this clock. This is a low-swing active-low signal referenced to Vref.

I

Transmit clock. Outgoing acknowledge and read data packets are aligned

with this clock. This is a low-swing active-low signal referenced to Vref.

I

Logic threshold reference voltage for low swing signals.

Control signal to frame packets transmit part of the operation code to

I/O

acknowledge requests, and to interrupt (terminate) pending transactions.

This is a low-swing active-low signal referenced to Vref.

Control signal to manage the operating modes of the RDRAMs and to

I

transfer column addresses for random-access (non-sequential) transactions.

This is a low-swing active-low signal referenced to Vref.

+3.3V power supply. VddA is a separate analog supply for clock recovery

in the RDRAM.

Circuit ground. GndA is a separate analog ground for clock generation in

the RDRAM.

I

Initialization daisy chain input. TTL levels. Active high.

O

Initialization daisy chain output. TTL levels. Active high.

Mechanical

Pins

Pin 1

Pin 32

Mechanical

Pins

Fig. 5 SHP Package

6

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