MSM5718B70-60GS-K Ver la hoja de datos (PDF) - Oki Electric Industry

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MSM5718B70-60GS-K

18-Megabit RDRAM (2M x 9)

Oki Electric Industry 

MSM5718B70

¡ Semiconductor

Bank 7

Bank 8

Bank 5

Bank 6

Bank 3

Bank 1

Bank 4

Bank 2

RDRAM 4

RDRAM 3

Sense Amp Cache page 1 Sense Amp Cache page 2

Registers

Address Comparators

Clocking

Byte h

Byte g

Byte f

Byte e Rambus Channel

Byte d 9 bits every 2 ns

Byte c

Byte b

Byte a

abcde f gh

RDRAM 2

RDRAM 1

Rambus Interface Cell

• Macrocell in embedded array and standard cell libraries

• Converts Rambus channel small swing signals to ASIC-

core-compatible CMOS levels

• Converts 9 bits every 2 ns to 72 bits (X2) every 16 ns

• Contains PLLs

Fig. 3 Data Transfer on the Rambus Channel

The Rambus channel has thirteen high-speed Rambus Signaling Logic (RSL) I/O signals that are

used to transfer information at 2 nanosecond intervals. These signals use low voltage swings (logic

0 = 2.25 V, logic 1 = 1.55 V) to achieve high bus speeds. Two TTL level signals are used for initialization

and powerdown operation. Fourteen signals supply power and DC voltage references to the

RDRAM, and the remaining pins are No Connects (reserved for future expansion).

The Rambus interface is implemented on both master and slave devices. Rambus masters (ASIC

devices, memory controllers, graphics engines, peripheral chips, or microprocessors) are the only

devices capable of generating transaction requests. RDRAMs are slave devices and can respond to

requests from master devices.

Fig. 1 shows a typical physical implementation of a Rambus system. It includes a controller ASIC

that acts as the Channel master and a base set of RDRAMs soldered directly to the board. An

RSocket™ is included on the Channel for memory upgrade using RModule™ expansion cards.

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