CY7C1314V18-200BZC Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1314V18-200BZC Datasheet PDF : 25 Pages
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Application
Example[2]
PRELIMINARY
Memory
Controller
Q
Din
Add.
Cntr.
18
72
72
SRAM #1
D
Q
18
18
17
SRAM #4
D
Q
18
17
CY7C1310V18
CY7C1312V18
CY7C1314V18
VTERM = VREF
R = 50Ω
CLK/CLK (input)
CLK/CLK (output)
2
2
R = 50Ω
VT = VREF
Truth Table[ 3, 4, 5, 6, 7, 8]
Operation
K
Write Cycle:
L-H
Load address on the rising edge of K
clock; input write data on K and K
rising edges.
Read Cycle:
L-H
Load address on the rising edge of K
clock; wait one and a half cycle; read
data on C and C rising edges.
NOP: No Operation
L-H
Standby: Clock Stopped
Stopped
RPS
X
WPS
DQ
L
D(A + 00)at K(t) ↑
DQ
D(A + 01) at K(t) ↑
L
X
Q(A + 00) at C(t + 1)↑ Q(A + 01) at C(t + 2) ↑
H
H
High-Z
High-Z
X
X
Previous State
Previous State
Write Cycle Descriptions (CY7C1310V18 and CY7C1312V18) [3, 9]
BWS0 BWS1
K
K
Comments
L
L
L-H
– During the Data portion of a Write sequence :
CY7C1310V18 − both nibbles (D[7:0]) are written into the device,
CY7C1312V18 − both bytes (D[17:0]) are written into the device.
L
L
–
L-H During the Data portion of a Write sequence :
CY7C1310V18 − both nibbles (D[7:0]) are written into the device,
CY7C1312V18 − both bytes (D[17:0]) are written into the device.
Notes:
2. The above application shows 4 CY7C1312V18 being used. This holds true for CY7C1310V18 and CY7C1314V18 as well.
3. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge.
4. Device will power-up deselected and the outputs in a three-state condition.
5. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01 represents the internal address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
8. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 can be altered on different portions of a write cycle, as
long as the set-up and hold requirements are achieved.
Document #: 38-05180 Rev. *A
Page 8 of 25
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