CY7C1310V18-167BZC Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY7C1310V18-167BZC

18-Mb QDR™-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1310V18

CY7C1312V18

CY7C1314V18

Pin Definitions

Pin Name

D[x:0]

I/O

Input-

Synchronous

WPS

BWS0, BWS1,

BWS2, BWS3

Input-

Synchronous

Input-

Synchronous

A

Input-

Synchronous

Q[x:0]

RPS

C

C

K

K

CQ

CQ

Outputs-

Synchronous

Input-

Synchronous

Input-

Clock

Input-Clock

Input-Clock

Input-Clock

Echo Clock

Echo Clock

Pin Description

Data input signals, sampled on the rising edge of K and K clocks during valid

write operations.

CY7C1310V18 - D[7:0]

CY7C1312V18 - D[17:0]

CY7C1314V18 - D[35:0]

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When

asserted active, a write operation is initiated. Deasserting will deselect the Write port.

Deselecting the Write port will cause D[x:0] to be ignored.

Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K

and K clocks during write operations. Used to select which byte is written into the device

during the current portion of the write operations. Bytes not written remain unaltered.

CY7C1310V18 − BWS0 controls D[3:0] and BWS1 controls D[7:4].

CY7C1312V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].

CY7C1314V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]

and BWS3 controls D[35:27]

All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write

Select will cause the corresponding byte of data to be ignored and not written into the

device.

Address Inputs. Sampled on the rising edge of the K clock during active read and write

operations. These address inputs are multiplexed for both Read and Write operations.

Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310V18,

1M x 18 (2 arrays each of 512K x 18) for CY7C1312V18 and 256K x 36 (2 arrays each

of 256K x 36) for CY7C1314V18. Therefore, only 20 address inputs are needed to

access the entire memory array of CY7C1310V18, 19 address inputs for CY7C1312V18

and 18 address inputs for CY7C1314V18. These inputs are ignored when the appro-

priate port is deselected.

Data Output signals. These pins drive out the requested data during a Read operation.

Valid data is driven out on the rising edge of both the C and C clocks during Read

operations or K and K. when in single clock mode. When the Read port is deselected,

Q[x:0] are automatically three-stated.

CY7C1310V18 − Q[7:0]

CY7C1312V18 − Q[17:0]

CY7C1314V18 − Q[35:0]

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).

When active, a Read operation is initiated. Deasserting will cause the Read port to be

deselected. When deselected, the pending access is allowed to complete and the output

drivers are automatically three-stated following the next rising edge of the C clock. Each

read access consists of a burst of two sequential transfers.

Positive Output Clock Input. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Negative Output Clock Input. C is used in conjunction with C to clock out the Read

data from the device. C and C can be used together to deskew the flight times of various

devices on the board back to the controller. See application example for further details.

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

to the device and to drive out data through Q[x:0] when in single clock mode. All accesses

are initiated on the rising edge of K.

Negative Input Clock Input. K is used to capture synchronous inputs being presented

to the device and to drive out data through Q[x:0] when in single clock mode.

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

CQ is referenced with respect to C. This is a free running clock and is synchronized

to the output clock of the QDRTM-II. In the single clock mode, CQ is generated with

respect to K. The timings for the echo clocks are shown in the AC timing table.

Document #: 38-05180 Rev. *A

Page 5 of 25

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