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CY7C1310V18-200BZC

18-Mb QDR™-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1310V18

CY7C1312V18

CY7C1314V18

18-Mb QDR™-II SRAM Two-word

Burst Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

• 167-MHz Clock for High Bandwidth

• Two-word Burst on all accesses

• Double Data Rate (DDR) interfaces on both Read & Write

Ports (data transferred at 333 MHz) @ 167MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatches

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x8, x18, and x36 configurations

• 1.8V core power supply with HSTL Inputs and Outputs

• 13x15 mm 1.0-mm pitch FBGA package, 165 ball (11x15

matrix)

• Variable drive HSTL output buffers

• Extended HSTL output voltage (1.4V–VDD)

• JTAG Interface

• On-chip Delay Lock Loop (DLL)

Configurations

CY7C1310V18 – 2M x 8

CY7C1312V18 – 1M x 18

CY7C1314V18 – 512K x 36

Logic Block Diagram (CY7C1310V18)

D[7:0] 8

The CY7C1310V18/CY7C1312V18/CY7C1314V18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR™-II archi-

tecture. QDRTM-II architecture consists of two separate ports

to access the memory array. The Read port has dedicated

Data Outputs to support Read operations and the Write Port

has dedicated Data Inputs to support Write operations.

QDRTM-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K clock.

Accesses to the QDRTM-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with two 8-bit words (CY7C1310V18) or 18-bit

words (CY7C1312V18) or 36-bit words (CY7C1314V18) that

burst sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising edge of

both input clocks (K/K and C/C), memory bandwidth is

maximized while simplifying system design by eliminating bus

“turn-arounds.”

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C/C (or K/K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

A(19:0)

20

Address

Register

Write

Reg

Write

Reg

Address

Register

20 A(19:0)

K

K

CLK

Gen.

VREF

WPS

BWS[1:0]

Control

Logic

Read Data Reg.

16 8

8

Control

Logic

Reg.

Reg.

Reg. 8

8

RPS

C

C

CQ

CQ

8

Q[7:0]

Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600

Document #: 38-05180 Rev. *A

Revised August 2, 2002

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