CY7C1312V18-133BZC Ver la hoja de datos (PDF) - Cypress Semiconductor

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Fabricante

CY7C1312V18-133BZC

18-Mb QDR™-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

CY7C1310V18

CY7C1312V18

CY7C1314V18

Write Cycle Descriptions (CY7C1314V18) (continued)[3, 9]

BWS0

BWS1

BWS2

BWS3

K

K

H

H

H

L

-

L-H

H

H

H

H

L-H

-

H

H

H

H

-

L-H

Comments

During the Data portion of a Write sequence, only

the byte (D[35:27]) is written into the device. D[26:0]

will remain unaltered.

No data is written into the device during this portion

of a write operation.

No data is written into the device during this portion

of a write operation.

Document #: 38-05180 Rev. *A

Page 10 of 25

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