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CY7C1318V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

Write Cycle Descriptions (CY7C1320V18) (continued)[3, 9]

H

L

H

H

–

L-H

H

H

L

H

L-H

–

H

H

L

H

–

L-H

H

H

H

L

L-H

H

H

H

L

–

L-H

H

H

H

H

L-H

–

H

H

H

H

–

L-H

CY7C1316V18

CY7C1318V18

CY7C1320V18

During the Data portion of a Write sequence,

only the byte (D[17:9]) is written into the

device. D[8:0] and D[35:18] will remain

unaltered.

During the Data portion of a Write sequence,

only the byte (D[26:18]) is written into the

device. D[17:0] and D[35:27] will remain

unaltered.

During the Data portion of a Write sequence,

only the byte (D[26:18]) is written into the

device. D[17:0] and D[35:27] will remain

unaltered.

During the Data portion of a Write sequence,

only the byte (D[35:27]) is written into the

device. D[26:0] will remain unaltered.

During the Data portion of a Write sequence,

only the byte (D[35:27]) is written into the

device. D[26:0] will remain unaltered.

No data is written into the device during this

portion of a write operation.

No data is written into the device during this

portion of a write operation.

Document #: 38-05177 Rev. *A

Page 9 of 24

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