CY7C1318V18 Ver la hoja de datos (PDF) - Cypress Semiconductor

Número de pieza

componentes Descripción

Fabricante

CY7C1318V18

18-Mb DDR-II SRAM Two-word Burst Architecture

Cypress Semiconductor 

PRELIMINARY

Burst Address Table (CY7C1318V18 and

CY7C1320V18)

First Address (External)

X..X0

X..X1

Second Address (Internal)

X..X1

X..X0

CY7C1316V18

CY7C1318V18

CY7C1320V18

Write Cycle Descriptions (CY7C1316V18 and CY7C1318V18)[3, 9]

BWS0 BWS1 K

L

L L-H

L

L

–

L

H L-H

L

H

–

H

L L-H

H

L

–

H

H L-H

H

H

–

K

Comments

– During the Data portion of a Write sequence :

CY7C1316V18 − both nibbles (D[7:0]) are written into the device,

CY7C1318V18 − both bytes (D[17:0]) are written into the device.

L-H During the Data portion of a Write sequence :

CY7C1316V18 − both nibbles (D[7:0]) are written into the device,

CY7C1318V18 − both bytes (D[17:0]) are written into the device.

– During the Data portion of a Write sequence :

CY7C1316V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,

CY7C1318V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.

L-H During the Data portion of a Write sequence :

CY7C1316V18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered,

CY7C1318V18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered.

– During the Data portion of a Write sequence :

CY7C1316V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,

CY7C1318V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.

L-H During the Data portion of a Write sequence :

CY7C1316V18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered,

CY7C1318V18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered.

– No data is written into the devices during this portion of a write operation.

L-H No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions (CY7C1320V18) [3, 9]

BWS0

BWS1

BWS2

BWS3

K

L

L

L

L

L-H

K

Comments

–

During the Data portion of a Write sequence,

all four bytes (D[35:0]) are written into the

device.

L

L

L

L

–

L-H During the Data portion of a Write sequence,

all four bytes (D[35:0]) are written into the

device.

L

H

H

H

L-H

–

During the Data portion of a Write sequence,

only the lower byte (D[8:0]) is written into the

device. D[35:9] will remain unaltered.

L

H

H

H

–

L-H During the Data portion of a Write sequence,

only the lower byte (D[8:0]) is written into the

device. D[35:9] will remain unaltered.

H

L

H

H

L-H

–

During the Data portion of a Write sequence,

only the byte (D[17:9]) is written into the

device. D[8:0] and D[35:18] will remain

unaltered.

Note:

9. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1316V18 and CY7C1318V18 and also

BWS2, BWS3 in the case of CY7C1320V18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.

Document #: 38-05177 Rev. *A

Page 8 of 24

Share Link: