CY7C1316V18 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1316V18 Datasheet PDF : 24 Pages
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PRELIMINARY
Pin Configurations (continued)
CY7C1320V18 (512K x 36) - 11 x 15 FBGA
1
2
3
4
5
6
7
8
A
CQ VSS/144M NC/36M R/W
BWS2
K
BWS1
LD
B
NC
DQ27 DQ18
A
BWS3
K
BWS0
A
C
NC
NC
DQ28
VSS
A
A0
A
VSS
D
NC
DQ29 DQ19
VSS
VSS
VSS
VSS
VSS
E
NC
NC
DQ20 VDDQ
VSS
VSS
VSS
VDDQ
F
NC
DQ30 DQ21 VDDQ
VDD
VSS
VDD
VDDQ
G
NC
DQ31 DQ22 VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
DQ32 VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
DQ23 VDDQ
VDD
VSS
VDD
VDDQ
L
NC
DQ33 DQ24 VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
N
NC
DQ35 DQ25
VSS
A
A
A
VSS
P
NC
NC
DQ26
A
A
C
A
A
R
TDO
TCK
A
A
A
C
A
A
CY7C1316V18
CY7C1318V18
CY7C1320V18
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
VSS/72M
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input/Output- Data input/Output signals. Inputs are sampled on the rising edge of K and K clocks during valid
Synchronous write operations. These pins drive out the requested data during a Read operation. Valid data is
driven out on the rising edge of both the C and C clocks during Read operations or K and K when
in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated.
CY7C1316V18 − DQ[7:0]
CY7C1318V18 − DQ[17:0]
CY7C1320V18− DQ[35:0]
Input- Synchronous load. This input is brought LOW when a bus cycle sequence is to be defined. This
Synchronous definition includes address and read/write direction. All transactions operate on a burst of 2 data.
BWS0, BWS1,
BWS2, BWS3
Input- Byte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1311V18 − BWS0 controls D[3:0] and BWS1 controls D[7:4].
CY7C1313V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1315V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select
will cause the corresponding byte of data to be ignored and not written into the device.
A, A0
Input- Address inputs. These address inputs are multiplexed for both Read and Write operations.
Synchronous Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1316V18, 1M x
18 (2 arrays each of 512K x 18) for CY7C1318V18 and 512K x 36 (2 arrays each of 256K x 36)
for CY7C1320V18.
CY7C1316V18 – Since the least significant bit of the address internally is a “0,” only 20 external
address inputs are needed to access the entire memory array.
CY7C1318V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 20 address inputs are needed to access the entire memory array.
CY7C1320V18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 19 address inputs are needed to access the entire memory array. All the dress inputs
are ignored when the appropriate port is deselected.
Document #: 38-05177 Rev. *A
Page 4 of 24
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