R2S15903SP
Preliminary
I2C Bus Format
MSB
LSB
MSB
LSB
MSB
LSB
S
Slave Address
A
Sub Address
A
Data
A
P
1 bit
8bit
1 bit
8bit
1 bit
8bit
1 bit
1bit
S: Starting Term
A: Acknowledge Bit
P: Stop Term
If more than one Data Byte is transmitted, then the significant SUB ADDRESS bits are auto incremented.
00H → 01H → 02H → 03H → 04H → 05H → 00H
1. Slave Address
MSB
LSB
1
0
0
0
0
0
1
R/WB
R/WB = 0: Write mode for register setting
R/WB = 1: Not available
2. Sub Address Table
Sub
address
D7
00H
01H
D6
D5
Lch VOL<H>
Rch VOL<H>
02H
Input selector
03H
04H
AGC/
05H
Bypass
Bass
Treble
AGC level
BIT
D4
D3
Rec output
AGC
mode
0
D2
D1
D0
Lch VOL<L>
Rch VOL<L>
Output
gain
Lch mute Rch mute
Surround
level
Mode selector
Rec gain
0
0
0
0
0
3. Data Table
<1> Master Volume Control (Sub Address: 00H, 01H)
VOL
ATT
(dB)
D7
0
0
–10
0
–20
0
–30
0
–40
0
–50
0
–60
0
–70
0
–80
1
VOL<H>
D6
D5
D4
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
VOL
ATT
(dB)
D3
0
0
–1
0
–2
0
–3
0
–4
0
–5
0
–6
0
–7
0
–8
1
–9
1
VOL<L>
D2
D1
D0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
Rev.1.4 Dec 06, 2005 page 8 of 11