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MAC7100 Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
Electrical Characteristics
3.10.2 ATD Accuracy
Table 27 and Table 28 specify the ATD conversion performance excluding any errors due to current
injection, input capacitance and source resistance.
Table 27. ATD Conversion Performance in 5 V Range
Conditions shown in Table 6 unless otherwise noted.
VREF = VRH – VRL = 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Q1 P 10-bit Resolution
LSB
—
5
—
Q2 P 10-bit Differential Nonlinearity
DNL
–1
—
1
Q3 P 10-bit Integral Nonlinearity
Q4 P 10-bit Absolute Error 1
INL
–2.5
±1.5
2.5
AE
–3
±2.0
3
Q5 P 8-bit Resolution
LSB
—
20
—
Q6 P 8-bit Differential Nonlinearity
DNL
–0.5
—
0.5
Q7 P 8-bit Integral Nonlinearity
Q8 P 8-bit Absolute Error 1
INL
–1.0
±0.5
1.0
AE
–1.5
±1.0
1.5
1 These values include the quantization error which is inherently 1/2 count for any A/D converter.
Unit
mV
Counts
Counts
Counts
mV
Counts
Counts
Counts
Table 28. ATD Conversion Performance in 3.3 V Range
Conditions shown in Table 6 unless otherwise noted.
VREF = VRH – VRL = 5.12 V, resulting in one 8 bit count = 20 mV and one 10 bit count = 5 mV
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
R1 P 10-bit Resolution
LSB
—
3.25
—
R2 P 10-bit Differential Nonlinearity
DNL
–1.5
—
1.5
R3 P 10-bit Integral Nonlinearity
R4 P 10-bit Absolute Error 1
INL
–3.5
±1.5
3.5
AE
–5
±2.0
5
R5 P 8-bit Resolution
LSB
—
13
—
R6 P 8-bit Differential Nonlinearity
DNL
–0.5
—
0.5
R7 P 8-bit Integral Nonlinearity
R8 P 8-bit Absolute Error 1
INL
–1.5
±1.0
1.5
AE
–1.5
±1.0
1.5
1 These values include the quantization error which is inherently 1/2 count for any A/D converter.
Unit
mV
Counts
Counts
Counts
mV
Counts
Counts
Counts
For the following definitions see also Figure 8.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps.
DNL(i) = V-----i--–-----V----i--–----1- – 1
1 LSB
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
∑ INL(n) =
DNL(i) = V-----n----–----V-----0- – n
1 LSB
i=1
25
MAC7100 Microcontroller Family Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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Go to: www.freescale.com
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