M95512-DR Ver la hoja de datos (PDF) - STMicroelectronics

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M95512-DR

512 Kbit serial SPI bus EEPROM with high-speed clock

STMicroelectronics 

Description

1

Description

M95512-W, M95512-R

The M95512-W, M95512-R and M95512-DR are electrically erasable programmable

memory (EEPROM) devices accessed by a high-speed SPI-compatible bus. In the rest of

the document these devices are referred to as M95512, unless otherwise specified.

The M95512-DR also offers an additional page, named the Identification Page (128 bytes)

which can be written and (later) permanently locked in Read-only mode. This Identification

Page offers flexibility in the application board production line, as it can be used to store

unique identification parameters and/or parameters specific to the production line.

Figure 1. Logic diagram

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3

7

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1

-

633

AI

The memory array is organized as 65536 × 8 bit. The device is accessed by a simple serial

interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 1 and

Figure 1.

The device is selected when Chip Select (S) is taken low. Communications with the device

can be interrupted using Hold (HOLD).

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Doc ID 11124 Rev 13

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