M27C1024-20B7TR Ver la hoja de datos (PDF) - STMicroelectronics

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M27C1024-20B7TR

1 Mbit (64Kb x16) UV EPROM and OTP EPROM

STMicroelectronics 

M27C1024

Figure 8. Programming and Verify Modes AC Waveforms

A0-A15

Q0-Q15

VPP

VCC

E

P

G

tAVPL

DATA IN

tQVPL

VALID

tPHQX

DATA OUT

tVPHPL

tGLQV

tVCHPL

tELPL

tPLPH

tQXGL

PROGRAM

VERIFY

tGHQZ

tGHAX

AI00706

Figure 9. Programming Flowchart

VCC = 6.25V, VPP = 12.75V

n=0

NO

++n

= 25

YES

P = 100µs Pulse

NO

VERIFY

YES

++ Addr

FAIL

Last NO

Addr

YES

CHECK ALL WORDS

1st: VCC = 6V

2nd: VCC = 4.2V

AI00707C

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows pro-

gramming of the whole array with a guaranteed

margin, in a typical time of 6.5 seconds. Program-

ming with PRESTO II consists of applying a se-

quence of 100µs program pulses to each word

until a correct verify occurs (see Figure 9). During

programming and verify operation, a MARGIN

MODE circuit is automatically activated in order to

guarantee that each cell is programmed with

enough margin. No overprogram pulse is applied

since the verify in MARGIN MODE provides nec-

essary margin to each programmed cell.

Program Inhibit

Programming of multiple M27C1024s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the parallel

M27C1024 may be common. A TTL low level

pulse applied to a M27C1024's P input, with E low

and VPP at 12.75V, will program that M27C1024.

A high level E input inhibits the other M27C1024s

from being programmed.

Program Verify

A verify (read) should be performed on the pro-

grammed bits to determine that they were correct-

ly programmed. The verify is accomplished with E

and G at VIL, P at VIH, VPP at 12.75V and VCC at

6.25V.

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