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M24512-WMW6T

512 Kbit Serial I²C Bus EEPROM

STMicroelectronics 

M24512

SUMMARY DESCRIPTION

These I2C-compatible electrically erasable pro-

grammable memory (EEPROM) devices are orga-

nized as 64K x 8 bits.

Figure 2. Logic Diagram

VCC

3

E0-E2

SCL

WC

M24512

SDA

VSS

AI02275

Table 2. Signal Names

E0, E1, E2

Chip Enable

SDA

Serial Data

SCL

Serial Clock

WC

Write Control

VCC

Supply Voltage

VSS

Ground

I2C uses a two-wire serial interface, comprising a

bi-directional data line and a clock line. The devic-

es carry a built-in 4-bit Device Type Identifier code

(1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are initiat-

ed by a Start condition, generated by the bus mas-

ter. The Start condition is followed by a Device

Select Code and Read/Write bit (RW) (as de-

scribed in Table 3.), terminated by an acknowl-

edge bit.

When writing data to the memory, the device in-

serts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Power On Reset

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. At Power-up, the

device will not respond to any command until VCC

has reached the Power On Reset threshold volt-

age (this threshold is lower than the VCC min oper-

ating voltage defined in Tables 8 and 9). In the

same way, as soon as VCC drops from the normal

operating voltage, below the Power On Reset

threshold voltage, the device stops to respond to

any command.

Prior to selecting and issuing commands to the

memory, a valid and stable VCC voltage must be

applied. This voltage must remain stable and valid

until the end of the transmission of the command

and, for a Write instruction, until the completion of

the internal write cycle (tW).

Figure 3. DIP, SO and TSSOP Connections

E0

E1

E2

VSS

M24512

1

8

2

7

3

6

4

5

AI04035B

VCC

WC

SCL

SDA

Note: See PACKAGE MECHANICAL section for package dimen-

sions, and how to identify pin-1.

4/24

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