KM732V595A Ver la hoja de datos (PDF) - Samsung
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KM732V595A Datasheet PDF : 15 Pages
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KM732V595A/L
PRELIMINARY
32Kx32 Synchronous SRAM
AC TIMING CHARACTERISTICS
(VDD=3.3V±5%, VDDQ=2.5V+0.4V/-0.13V, TA=0 to 70°C)
Parameter
KM732V595A-6 KM732V595A-7 KM732V595A-8 KM732V595A-10
Symbol
Unit
Min Max Min Max Min Max Min Max
Cycle Time
tCYC
6.6
-
7.5
-
8.6
-
10
-
ns
Clock Access Time
tCD
-
4.4
-
5.0
-
5.0
-
5.5
ns
Output Enable to Data Valid
tOE
-
4.8
-
4.8
-
5.0
-
5.5
ns
Clock High to Output Low-Z
tLZC
0
-
0
-
0
-
0
-
ns
Output Hold from Clock High
tOH
1.5
-
1.5
-
1.5
-
2.0
-
ns
Output Enable Low to Output Low-Z
tLZOE
0
-
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
tHZOE
-
4.0
-
4.0
-
4.0
-
4.0
ns
Clock High to Output High-Z
tHZC
1.5 5.0 1.5 5.0 1.5 5.0
1.5
5.0
ns
Clock High Pulse Width
tCH
2.5
-
2.5
-
2.5
-
3.0
-
ns
Clock Low Pulse Width
tCL
2.5
-
2.5
-
2.5
-
3.0
-
ns
Address Setup to Clock High
tAS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Status Setup to Clock High
tSS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Data Setup to Clock High
tDS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Write Setup to Clock High (GW, BW, WEX)
tWS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Advance Setup to Clock High
tADVS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Chip Select Setup to Clock High
tCSS
2.0
-
2.0
-
2.0
-
2.0
-
ns
Address Hold from Clock High
tAH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Status Hold from Clock High
tSH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Data Hold from Clock High
tDH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Write Hold from Clock High (GW, BW, WEX)
tWH
0.5
-
0.5
-
0.5
-
0.5
-
ns
Address Advance Hold from Clock High tADVH 0.5
-
0.5
-
0.5
-
0.5
-
ns
Chip Select Hold from Clock High
tCSH
0.5
-
0.5
-
0.5
-
0.5
-
ns
ZZ High to Power Down
tPDS
2
-
2
-
2
-
2
-
cycle
ZZ Low to Power Up
tPUS
2
-
2
-
2
-
2
-
cycle
NOTE : 1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and CS
is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
-8-
May 1997
Rev 1.0
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