KM732V595A Ver la hoja de datos (PDF) - Samsung
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KM732V595A Datasheet PDF : 15 Pages
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KM732V595A/L
PRELIMINARY
32Kx32 Synchronous SRAM
32Kx32-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• Core Supply Voltage : 3.3V±5%
• 5V Tolerant Inputs except I/O Pins
• I/O Supply Voltage : 2.5V+0.4/-0.13V.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a
linear burst.
• Three Chip Enables for simple depth expansion with No Data
Contention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A
FAST ACCESS TIMES
Parameter
Cycle Time
Symbol -6 -7 -8 -10 Unit
tCYC 6.6 7.5 8.6 10 ns
GENERAL DESCRIPTION
The KM732V595A/L is a 1,048,576 bit Synchronous Static
Random Access Memory designed for high performance sec-
ond level cache of Pentium and Power PC based System.
It is organized as 32K words of 32bits and integrates address
and control registers, a 2-bit burst address counter and added
some new functions for high performance cache RAM applica-
tions; GW, BW, LBO, ZZ.
Write cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is per-
formed by the combination of WEx and BW when GW is high.
And with CS1 high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status pro-
cessor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated internally in
the system′s burst sequence and are controlled by the burst
address advance(ADV) input.
LBO pin is DC operated and determines burst sequence (linear
or interleaved).
ZZ pin controls Power Down State and reduces Stand-by cur-
rent regardless of CLK.
The KM732V595A/L is fabricated using SAMSUNG′s high per-
formance CMOS technology and is available in a 100pin TQFP
package. Multiple power and ground pins are utilized to mini-
mize ground bounce.
Clock Access Time
tCD 4.4 5.0 5.0 5.5 ns
Output Enable Access Time tOE 4.8 4.8 5.0 5.5 ns
LOGIC BLOCK DIAGRAM
CLK
LBO
ADV
ADSC
BURST CONTROL
LOGIC
ADSP
CS1
CS2
CS2
GW
BW
WEa
WEb
WEc
WEd
OE
ZZ
DQa0 ~ DQd7
A0~A14
CONTROL
LOGIC
BURST
ADDRESS
COUNTER
A′0~A′1
A0 ~ A1
ADDRESS
REGISTER
A2~A14
32Kx32
MEMORY
ARRAY
DATA-IN
REGISTER
OUTPUT
REGISTER
BUFFER
-2-
May 1997
Rev 1.0
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