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KAC-1310 Datasheet PDF : 76 Pages
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IMAGE SENSOR SOLUTIONS
IMAGE SENSOR SOLUTIONS
Exposure Gain PGA (Exp Gain A/B)
The Exposure (Global) Gain consists of two Gain
stages (A and B) in series. Each of these gain
stages has a Raw and Lin1 mode as described in
the previous WB Gain section. Thus all colors can
be amplified by the value in Exp GainA (reg 10h)
and then again by Exp GainB (reg 21h) to
compensate for varying exposure of the scene.
The easiest way to implement this is to program
Exp GainB at unity and then adjust Exp GainA
until it is at its maximum of 2.7395x. Then
increase the Exp GainB until the final exposure
gain is reached. The gains of the two Exp Gain
stages are controlled by Registers 10h and 21h,
(Table 21 and Table 24 on pages 49 and 52). The
Exp Gain Mode is defined in Register 22h, (Table
25 on page 53).
The dual gain-stage implementation of the Exp
Gain may cause difficulty in some auto-exposure
routines; this can be avoided by setting the Exp
Gain to Lin2 Mode. In Lin2 Mode, Reg 10h is used
to set both gain stages in an attempt to give
uniform gain steps across the entire 7.5x range of
the two Exp Gain stages. Only one register is
used to simplify user programming, and thus the
gain step size is increased to ~0.11119 to allow
the full range to be accessed by a single 6-bit
register. Note that the gain step size is almost but
not completely uniform. Any one step may deviate
from the mean step size of 0.11119 by a small
amount.
Global Digital Offset Voltage Adjust
(GDOVA)
A programmable global offset adjustment is
available on the KAC-1310. A user defined offset
value is loaded via a 6-bit signed magnitude
programming code via the ADC DOVA Register,
(Table 26 on page 54).
Offset correction allows fine-tuning of the signal to
remove any additional residual error, which may
have accumulated in the analog signal path. This
function is performed directly before analog to
digital conversion and allows the user to set the
‘black’ level in the ADC range.
Analog to Digital Converter (ADC)
The ADC is a fully differential, low power circuit. A
pipe-lined, Redundant Signed Digit (RSD)
algorithmic technique is used to yield an ADC with
superior characteristics for imaging applications.
Integral Noise Linearity (INL) and Differential
Noise Linearity (DNL) performance is specified at
±1.0 and ±0.5, respectively, with no missing
codes. The input dynamic range of the ADC is
programmed via a Programmable Voltage
Reference Generator. The positive reference
voltage (VREFP) and negative reference voltages
(VREFM) can be programmed from 2.5V to 1.25V
and 0V to 1.25V respectively in steps of 5mV via
the Reference Voltage Registers (Table 17 and
Table 18 on page 46). This feature is used
independently or in conjunction with the PGAs to
maximize the system dynamic range based on
incident illumination. The default input range for
the ADC is 1.86V for VREFP and 0.59V for
VREFM hence allowing a 10-bit digitization of a
1.3V peak-to-peak signal.
mV
10dn
=
2(V + −V − )
1024
=
2(1.86 − 0.59)
1024
=
2.48
mV
10dn
If the 20x gain provided by the PGAs is not
sufficient, the ADC references can be used to
apply additional gain to the ASP. To increase the
gain the ADC references need to be moved closer
to Vcm (1.25V). This should be used only after the
PGAs have been used to their fullest since moving
the ADC references too far will degrade the ADC
performance. The effective gain of the ADC block
will be:
Gain =
2.48
2(V + −V − )
1024
Ex. If Reg 0Ah=Reg 0Bh≡BAh then the ADC Gain =
2.
Gain =
2.48
2(1.57 − 0.93)
= 1.98
1024
The user should connect 0.1 µF capacitors to
CVREFP (pin 15) and CVREFM (pin 14) (see
Figure 2) to accurately hold the biases.
20
KAC-1310 Rev 4 • www.kodak.com/go/imagers 585-722-4385 Email: imagers@kodak.com
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