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KAC-1310 Datasheet PDF : 76 Pages
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IMAGE SENSOR SOLUTIONS
IMAGE SENSOR SOLUTIONS
ANALOG SIGNAL PROCESSING CHAIN
(ASP)
The KAC-1310’s analog signal processing (ASP)
chain incorporates Correlated Double Sampling
(CDS), Frame Rate Clamp (FRC), two Digitally
Programmable Gain Amplifiers (DPGA), Offset
Correction (DOVA), and a 10-bit Analog to Digital
Converter (ADC). See Figure 3 for a block
diagram of the ASP chain.
Correlated Double Sampling (CDS)
The uncertainty associated with the reset action of
a capacitive node results in a reset noise which is
proportional to kTC; ‘C’ being the capacitance of
the node, ‘T’ the temperature, and ‘k’ the
Boltzmann constant. A common way of
eliminating this noise source in all image sensors
is to use Correlated Double Sampling. The output
signal is sampled twice, once for its reset
(reference) level and once for the actual video
signal. These values are sampled and held while
a difference amplifier subtracts the reference level
from the signal output. Double sampling of the
signal eliminates correlated noise sources.
Pixel
Output
S&H Reset
+
V+
Diff
OpAmp
-
V-
S&H Signal
Figure 10: Conceptual block diagram of CDS
Cap FRCA
0.1µF
CFRCA
FRCLMP
FRCLMP
1x
Previous
+
BUF
-
Stage
+
VCM
Diff
-
VCM
V+
V-
FRCLMP
1x
FRCLMP
+
BUF
-
VCM
Cap FRCB
0.1µF
CFRCB
Figure 11: FRC Conceptual Block Diagram
processed and held to establish pixel reference
level at the CFRCA and CFRCB pins. During this
period, the FRC’s differential outputs (V+ and V- on
the Diff Amp) shown in Figure 11 are clamped to
Vcm. Together, these actions help to eliminate the
dark level offset, simultaneously establishing the
desired zero code at the ADC output. The user
can disable the FRC via the Clamp Control and
HCLK Delay Register (64h), (Table 50 on page 68)
which allows the ASP chain to drift in offset. If the
FRC is disabled, it is recommended that the
CFRCA and CFRCB pins be grounded. Care
should be exercised in choosing the capacitors for
the CFRCA and CFRCB pins to reflect different
Frame Rates. For small WOI or fast Frame Rates,
a smaller capacitor may be used.
Frame Rate Clamp (FRC)
The FRC (Figure 11) is designed to provide a
feed-forward dark level compensation. In the
automatic FRC mode, the optical black level
reference is reestablished each time that the
image sensor begins a new frame. The KAC-1310
uses optical black (dark) pixels to establish this
reference.
The dark pixel sample period is automatically
controlled internally and it is set to skip the first 3
dark rows and then sample the next 2 dark rows.
When “dark clamping” is active, each dark pixel is
Column Digital Offset Voltage Adjust
(CDOVA)
A programmable per-column offset adjustment is
available on the KAC-1310. There are 64
registers that can be programmed with an offset
that is added to each 64th column (Mod64 Column
Offset Registers; Table 52 on page 70). Each
register is 6 bits, (5 bits plus 1 sign bit), providing
±32 register values. This set of 64 values is then
repeatedly applied to each bank of 64 columns in
the sensor via the column DOVA stage of the ASP
chain.
In addition to the per-column offset, there is a
global column offset that can be added to every
column. This is used to remove any variation of
the dark level with respect to varying gain. The
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KAC-1310 Rev 4 • www.kodak.com/go/imagers 585-722-4385 Email: imagers@kodak.com
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