Data Sheet
INDT/R165B
INDT/R330B
3.8 Timing Specification
(a) Transmitter pixel interface
t1
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
PX_VSYNC
t2
Figure 3.4: Pixel Interface Timing Diagram At Rising Edge At Tx
Parameter
t1
t2
Description
Pixel data and ctrl signal setup time to pixel clock at Tx
Pixel data and ctrl signal hold time to pixel clock at Tx
Min.
Typ.
0.5
0.9
1.0
1.3
Table 3.10: Pixel Interface Timing Table At Rising Edge At Tx
Max. Unit
-
ns
-
ns
t3
PCLK+
PX_D[47:0],
PX_DE,
PX_HSYNC,
t4
PX_VSYNC
Figure 3.5: Pixel Interface Timing Diagram At One Pixel Per Clock At Falling Edge At Tx
Parameter
t3
t4
Description
Pixel data and ctrl signal setup time to pixel clock at Tx
Pixel data and ctrl signal hold time to pixel clock at Tx
Min.
Typ.
Max. Unit
0.5
0.9
-
ns
0.5
1.3
-
ns
Table 3.11: Pixel Interface Timing Table At One Pixel Per Clock At Falling Edge At Tx
Date: 2005-02-18 Revision: 1.1
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