INDT165B Ver la hoja de datos (PDF) - Unspecified

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Fabricante

INDT165B

Long Distance Digital Display Link Transmitter & Receiver

Unspecified 

Data Sheet

INDT/R165B

INDT/R330B

2.3 Interface Configuration Scheme

Note: The low-speed downstream sideband is automatically enabled, when high-speed downstream sideband OR audio is

enabled. INDT and INDR must be configured within the same group.

Interface

Vector

Name

Pixel

Interface

cfg0

Sideband

Interface

Tx

cfg1

Audio +

High Speed

Upstream

SB1

cfg2

Pre-

Emphasis

For

Serial

Upstream

Trans-

mission

cfg3

Vector

Bits

1100

1101

1110

0011

1111

0100

0101

1001

1010

0000

0001

0010

0110

0111

0000

11XX

1100

1111

1110

X100

X111

01XX

11XX

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Pixel Interface

12-bit (Tx only)

12-bit (Tx only)

12-bit (Tx only)

12-bit (Tx only)

24-bit

24-bit

24-bit

48-bit

48-bit

18-bit

18-bit

18-bit

36-bit

36-bit

Tx only

Rx only

Description

12 bits low part of pixel(n) @ rising edge of PX_CLK+

12 bits high part of pixel(n) @ falling edge of PX_CLK+

12 bits low part of pixel(n) @ falling edge of PX_CLK+

12 bits high part of pixel(n) @ rising edge of PX_CLK+

12 bits low part of pixel(n) @ rising edge of PX_CLK+

12 bits high part of pixel(n) @ rising edge of PX_CLK-

12 bits low part of pixel(n) @ rising edge of PX_CLK-

12 bits high part of pixel(n) @ rising edge of PX_CLK+

24 bits of pixel(n) sampled at rising edge of PX_CLK+

24 bits of pixel(n) sampled at falling edge of PX_CLK+

24 bits of pixel(n) sampled at both edges of PX_CLK+

24 bits of pixel(n) and

24 bits of pixel(n+1) sampled at rising edge of PX_CLK+

24 bits of pixel(n) and

24 bits of pixel(n+1) sampled at falling edge of PX_CLK+

18 bits of pixel(n) sampled at rising edge of PX_CLK+

18 bits of pixel(n) sampled at falling edge of PX_CLK+

18 bits of pixel(n) sampled at both edges of PX_CLK+

18 bits of pixel(n) and

18 bits of pixel(n+1) sampled at rising edge of PX_CLK+

18 bits of pixel(n) and

18 bits of pixel(n+1) sampled at falling edge of PX_CLK+

Disable high-speed downstream sideband data channel

SB3 and SB44

Enable high-speed downstream sideband data channel

SB3 and SB44

Clocking: Asynchronous mode at downstream sideband

data channels SB3 and SB44

Clocking: Synchronous mode at downstream sideband

data channels SB3 and SB44

Clocking: Sampling mode at downstream sideband data

channels SB3 and SB44

Disable upstream sideband data

Enable upstream sideband data

Disable Audio

Enable Audio

Inom = x1.0, Ipre = x1.3, algorithm 1

Inom = x1.0, Ipre = x1.3, algorithm 2

Inom = x1.0, Ipre = x1.6, algorithm 1

Inom = x1.0, Ipre = x1.6, algorithm 2

Inom = x1.0, Ipre = x1.9, algorithm 1

Inom = x1.0, Ipre = x1.9, algorithm 2

Inom = x1.3, Ipre = x1.6, algorithm 1

Inom = x1.3, Ipre = x1.6, algorithm 2

Inom = x1.3, Ipre = x1.9, algorithm 1

Inom = x1.3, Ipre = x1.9, algorithm 2

Inom = x1.6, Ipre = x1.9, algorithm 1

Inom = x1.6, Ipre = x1.9, algorithm 2

Inom = Ipre = x1.9

Inom = Ipre = x1.3

Inom = Ipre = x1.0

Inom = Ipre = x1.6

Group

V1

V2

S1

S2

A

Table 2.3: Configuration of the Pixel Interface Mode

4 Sideband Data Channel 4 (SB4) only available with INDT/R330B

Date: 2005-02-18 Revision: 1.1

Page 14 of 41

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