HY57V561620 Ver la hoja de datos (PDF) - Hynix Semiconductor
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HY57V561620 Datasheet PDF : 13 Pages
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HY57V561620(L)T
AC CHARACTERISTICS I
Parameter
System clock cycle
time
CAS Latency = 3
CAS Latency = 2
Clock high pulse width
Clock low pulse width
Access time from
clock
CAS Latency = 3
CAS Latency = 2
Data-out hold time
Data-Input setup time
Data-Input hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
Command setup time
Command hold time
CLK to data output in low Z-time
CLK to data output
in high Z-time
CAS Latency = 3
CAS Latency = 2
Symbol
tCK3
tCK2
tCHW
tCLW
tAC3
tAC2
tOH
tDS
tDH
tAS
tAH
tCKS
tCKH
tCS
tCH
tOLZ
tOHZ3
tOHZ2
-HP
Min Max
7.5
1000
10
2.5
-
2.5
-
-
5.4
-
6
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
2.7
5.4
3
6
-H
Min Max
7.5
1000
10
2.5
-
2.5
-
-
5.4
-
6
2.7
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1.5
-
0.8
-
1
-
2.7
5.4
3
6
-8
Min Max
8
1000
10
3
-
3
-
-
6
-
6
3
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
3
6
3
6
-P
Min Max
10
1000
10
3
-
3
-
6
6
3
-
2
-
1
-
2
-
1
-
2
-
1
-
2
-
1
-
1
-
3
6
3
6
-S
Min Max
Unit Note
10
ns
1000
12
ns
3
-
ns
1
3
-
ns
1
6
ns
2
6
ns
3
-
ns
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
2
-
ns
1
1
-
ns
1
1
-
ns
3
6
ns
3
6
ns
Note :
1. Assume tR / tF (input rise and fall time ) is 1ns.
2. Access times to be measured with input signals of 1v/ns slew rate, 0.8v to 2.0v
Revision 1.8 / Apr.01
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