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EM25LV512

512 K (64K x 8) Bits Serial Flash Memory

ELAN Microelectronics 

EM25LV512

512 K (64K x 8) Bits Serial Flash Memory

SPECIFICATION

Device Operation

The EM25LV512 uses Instruction to initiate the memory operation functions. The

Instructions are written to the device by asserting Serial Data In (D) input while keeping Chip

Select (S#) Low and are latched on the rising edge of Serial Clock(C).

Operation

S# Hold# W#

D

Q

Read

Write

VIL

VIH

VIH

X

Data Out

High Z /

VIL

VIH

VIH

Address/Data In

Status Register out

Standby

VIL

VIH

VIH

X

Deep Power Down Mode1 VIL

VIH

VIH

X

Hold

VIL

VIL

VIH

X

Write Protect 2

VIL

VIH

VIH

X

Status Register Write

Inhibit 3

VIL

VIH

VIL

X

High Z

High Z

High Z

High Z

High Z

Note: 1 See Table 7 for the Instruction Set of Deep Power Down Mode.

2 Write Protect is enabled with the Status Register parameter BP0 and BP1 (see Table 4).

3 Status Register Write Inhibit will be combined with Status Register Write Disable (SRWD) and

Write Protect (W#) (see Table 6).

Table 5: EM25LV512 Device Operation

Hold Function

The Hold (HOLD#) signal allows the EM25LV512 operation to be paused while it is actively

selected with S# at low. To enter into the Hold condition, the device must be selected with

Chip Select (S#) at Low. However, setting this Hold signal Low does not terminate any Write

Status Register, Program, or Erase cycle that is currently in progress.

The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this

coincides with Serial Clock (C) being at Low (shown in Figure 9). The Hold condition ends on

the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (C)

being at Low as well.

If the falling edge does not coincide with Serial Clock (C) being at Low, the Hold condition will

start when Serial Clock (C) goes Low. Similarly, if Serial Clock (C) is not at Low, the Hold

condition will end when Serial Clock (C) goes to Low (this is shown in Figure 9). During the

Hold condition, the Serial Data Output (Q) is at high impedance, and the Serial Data Input (D)

& Serial Clock (C) are Don’t Care.

Normally, the device is kept selected with Chip Select (S#) driven Low for the whole duration

of the Hold condition. This is to assure that the state of the internal logic remains unchanged

from the moment it enters the Hold condition.

This specification is subject to change without further notice. (11.08.2004 V1.0)

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