EM25LV512-25MS Ver la hoja de datos (PDF) - ELAN Microelectronics
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EM25LV512-25MS Datasheet PDF : 30 Pages
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EM25LV512
512 K (64K x 8) Bits Serial Flash Memory
SPECIFICATION
4 Chip Select (S#):
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance state. Unless an internal Program, Erase, or Write Status Register cycle is in
progress, the device will be in the Standby mode (this is not the Deep Power-down mode).
Driving Chip Select (S#) Low enables the device, and places it in the active power mode.
After Power-up, a falling edge on Chip Select (S#) is required prior to the start of any
instruction.
5 Write Protect (W#):
This input pin can be used to prevent the Status Register from being written and active low.
When used in conjunction with the Status Register’s Block Protect (BP1 and BP1) bits and
Status Register Protect (SRWD) bits, a portion of or the entire memory array can be hardware
protected.
6 Hold (HOLD#):
This input pin is used to pause any serial communications with the device without the need to
deselect the device. When HOLD# is brought low, the Serial Data Output (Q) is at high
impedance state, and Serial Data Input (D) & Serial Clock (C) are Don’t Care. To start the
Hold condition, the device must be selected with Chip Select (S#) driven Low.
SPI Modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
CPOL=0, CPHA=0
CPOL=1, CPHA=1
Under these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 2, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
This specification is subject to change without further notice. (11.08.2004 V1.0)
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