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CS48500

32-bit Audio Decoder DSP Family

Cirrus Logic 

CS48500 Data Sheet

32-bit Audio Decoder DSP Family

4. Hardware Functional Description

4.1 DSP Core

The CS48500 is a single-core DSP with separate X and Y data and P code memory spaces. The DSP

core is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing

two multiply-and-accumulate (MAC) operations per clock cycle. The DSP core has eight 72-bit

accumulators, four X- and four Y-data registers, and 12 index registers.

The DSP core is coupled to a flexible DMA engine. The DMA engine can move data between peripherals

such as the serial control port (SCP), digital audio input (DAI) and digital audio output (DAO), or any DSP

core memory, all without the intervention of the DSP. The DMA engine off loads data move instructions

from the DSP core, leaving more MIPS available for signal processing instructions.

CS48500 functionality is controlled by application codes that are stored in on-board ROM or downloaded

T to the CS48500 from a host controller or external serial FLASH/EEPROM.

F Users can develop their applications using DSP Composer to create the processing chain and then

compile the image into a series of commands that are sent to the CS48500 through the SCP. The

A processing application can either load modules (matrix-processors, virtualizers, post-processors) from

the DSPs on-board ROM, or custom firmware can be downloaded through the SCP.

R The CS48500 is suitable for a variety of audio post-processing applications such as automotive head-

D ends, automotive amplifiers, and boom boxes.

4.1.1 DSP Memory

L The DSP core has its own on-chip data and program RAM and ROM and does not require external

I memory for post-processing applications.

IA H The Y-RAM and P-RAM share a single block of memory that can be configured to make Y and P equal in

size, or more memory can be allocated for Y-RAM in 2kword blocks.

T P 4.1.2 DMA Controller

N L The powerful 8-channel DMA controller can move data between 8 on-chip resources. Each resource has

its own arbiter: X, Y, and P RAMs/ROMs and the peripheral bus. Modulo and linear addressing modes

E E are supported, with flexible start address and increment controls. The service intervals for each DMA

CONFID D channel, as well as up to 6 interrupt events, are programmable.

DS734A3

©Copyright 2006 Cirrus Logic, Inc.

9

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