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CS48500

32-bit Audio Decoder DSP Family

Cirrus Logic 

CS48500 Data Sheet

32-bit Audio Decoder DSP Family

4.2.6 Hardware Watchdog Timer

The CS48500 has an integrated watchdog timer that acts as a “health” monitor for the DSP. The

watchdog timer must be reset by the DSP before the counter expires, or the entire chip is reset. This

peripheral ensures that the CS48500 will reset itself in the event of a temporary system failure. In stand-

alone mode (i.e. no host mcu), the DSP will reboot from external FLASH. In slave mode (i.e. host mcu

present) a GPIO will be used to signal the host that the watchdog has expired and the DSP should be

rebooted and re-configured.

4.3 DSP I/O Description

4.3.1 Multiplexed Pins

Many of the CS48500 pins are multi-functional. For details on pin functionality please refer to the

CS48500 Hardware User’s Manual.

T 4.3.2 Termination Requirements

F Open-drain pins on the CS48500 must be pulled high for proper operation. Please refer to the CS48500

Hardware User’s Manual to identify which pins are open-drain and what value of pull-up resistor is

A required for proper operation.

R Mode select pins on the CS48500 are used to select the boot mode upon the rising edge from reset. A

detailed explanation of termination requirements for each communication mode select pin can be found

D in the CS48500 Hardware User’s Manual.

4.3.3 Pads

L I The CS48500 I/Os operate from the 3.3 V supply and are 5 V tolerant.

4.4 Application Code Security

IA H The external program code may be encrypted by the programmer to protect any intellectual property it

T P may contain. A secret, customer-specific key is used to encrypt the program code that is to be stored

CONFIDEN DEL external to the device. Please contact your local Cirrus representative for details.

DS734A3

©Copyright 2006 Cirrus Logic, Inc.

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CONFIDENTIAL

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