BU90R104 Ver la hoja de datos (PDF) - ROHM Semiconductor

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Fabricante

BU90R104

35bit LVDS Receiver 5:35 DeSerializer

ROHM Semiconductor 

BU90R104

Datasheet

●Pin Description

Pin Name

Pin No.

RA+, RA-

50,49

I/O

LVDS Input

Description

RB+, RB-

RC+, RC-

RD+, RD-

52,51

55,54

60,59

LVDS Input

LVDS data input

LVDS Input

+ : Positive input of LVDS data differential pair.

- : Negative input of LVDS data differential pair.

LVDS Input

RE+, RE-

62,61

LVDS Input

RCLK+, RCLK- 57,56

LVDS Input LVDS clock Input

RA6～RA0

RB6～RB0

RC6～RC0

RD6～RD0

RE6～RE0

40,41,42,43,

45,46,47

32,33,34,35,

36,38,39

22,24,25,26,

27,28,29

14,15,17,18,

19,20,21

6,7,8,10,

11,12,13

Output

Output

Output

Output

Output

LVCMOS data outputs.

RESERVE

2

PD

3

OE

4

R/F

VDD

5

9,23,37,48

Input

Input

Input

Input

Power

Reserved input must be “Low” for normal operation.

Power down input for the internal system.

H : Normal operation.

L : Power down (All output are “Low”).

Power down input for the data output driver.

H : Output enable (Normal operation).

L : Output disable (All outputs are “Hi-Z”).

Select input pin for data output clock triggering edge.

H : Output data is latched on rising edge.

L : Output data is latched on falling edge.

3.3V output driver and digital core power supply pin.

CLKOUT

31

Output LVCMOS level clock output.

GND

1,16,30,44

Ground Ground pin for both data output driver cells and the digital cores.

LVDD

53

Power Power supply pin for LVDS core.

LGND

58

Ground Ground pin for LVDS core.

PVDD

64

Power Power supply pin for PLL core.

PGND

.

63

Ground Ground pin for PLL core.

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TSZ22111・15・001

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TSZ02201-0L2L0H500030-1-2

27.Feb.2015 Rev.002

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