CY7C167A-15 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C167A-15 Datasheet PDF : 9 Pages
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CY7C167A
Capacitance[5]
Parameter
CIN
COUT
CCE
Description
Input Capacitance
Output Capacitance
Chip Enable Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
AC Test Loads and Waveforms
5V
OUTPUT
R1 329Ω
5V
OUTPUT
30 pF
R2
202Ω
5 pF
INCLUDING
JIG AND
SCOPE (a)
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
125Ω
1.9V
R1 329Ω
R2
202Ω
(b)
C167A-3
3.0V
10%
GND
< 5 ns
Max.
Unit
10
pF
10
pF
6
pF
ALL INPUT PULSES
90%
90%
10%
< 5 ns
C167A-4
Switching Characteristics Over the Operating Range[6]
7C167A-15 7C167A-20 7C167A-25 7C167A-35 7C167A-45
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
15
20
25
30
ns
tAA
Address to Data Valid
15
20
25
30
ns
tOHA
Data Hold from Address Change 5
5
5
5
5
ns
tACE
tLZCE
tHZCE
CE LOW to Data Valid
CE LOW to Low Z[7]
CE HIGH to High Z[7, 8]
15
20
25
35
45 ns
5
5
5
5
5
ns
8
8
10
15
15 ns
tPU
CE LOW to Power-Up
0
0
0
0
0
ns
tPD
CE HIGH to Power-Down
WRITE CYCLE[9]
15
20
20
20
25 ns
tWC
Write Cycle Time
15
20
20
25
40
ns
tSCE
CE LOW to Write End
12
15
20
25
30
ns
tAW
Address Set-Up to Write End
12
15
20
25
30
ns
tHA
Address Hold from Write End
0
0
0
0
0
ns
tSA
Address Set-Up to Write Start
0
0
0
0
0
ns
tPWE
WE Pulse Width
12
15
15
20
20
ns
tSD
Data Set-Up to Write End
10
10
10
15
15
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High Z[7, 8]
WE HIGH to Low Z[7]
0
0
0
0
0
ns
7
7
7
10
15 ns
5
5
5
5
5
ns
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
7. At any given temperature and voltage condition, tHZ is less than tLZ for any given device.
8. tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signal must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05027 Rev. **
Page 3 of 9
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