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M24164-BN1

16 Kbit Serial I²C Bus EEPROM with 1 Inverting and 2 Non-Inverting Chip Enable Lines

STMicroelectronics 

M24164

Figure 7. Write Mode Sequences with WC=1 (data write inhibited)

WC

Byte Write

ACK

ACK

NO ACK

DEV SEL

BYTE ADDR

DATA IN

R/W

WC

Page Write

WC (cont'd)

Page Write

(cont'd)

ACK

ACK

NO ACK

NO ACK

DEV SEL

BYTE ADDR DATA IN 1

DATA IN 2

DATA IN 3

R/W

NO ACK

NO ACK

DATA IN N

AI02803C

Write Operations

Following a Start condition the bus master sends

a Device Select Code with the RW bit reset to 0.

The device acknowledges this, as shown in Figure

8, and waits for an address byte. The device re-

sponds to the address byte with an acknowledge

bit, and then waits for the data byte.

Writing to the memory may be inhibited if Write

Control (WC) is driven High. Any Write instruction

with Write Control (WC) driven High (during a pe-

riod of time from the Start condition until the end of

the address byte) will not modify the memory con-

tents, and the accompanying data bytes are not

acknowledged, as shown in Figure 7.

When the bus master generates a Stop condition

immediately after the Ack bit (in the “10th bit” time

slot), either at the end of a Byte Write or a Page

Write, the internal memory Write cycle is triggered.

A Stop condition at any other time slot does not

trigger the internal Write cycle.

During the internal Write cycle, Serial Data (SDA)

is disabled internally, and the device does not re-

spond to any requests.

Byte Write

After the Device Select code and the address byte,

the bus master sends one data byte. If the ad-

dressed location is Write-protected, by Write Con-

trol (WC) being driven High, the device replies with

NoAck, and the location is not modified. If, instead,

the addressed location is not Write-protected, the

device replies with Ack. The bus master termi-

nates the transfer by generating a Stop condition,

as shown in Figure 8.

Page Write

The Page Write mode allows up to 16 bytes to be

written in a single Write cycle, provided that they

are all located in the same ’row’ in the memory:

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