UPD63310GK-9EU Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD63310GK-9EU

STEREO SOUND CODEC

NEC => Renesas Technology 

µPD63310

17:

D5

D4

D3

D2

D1

D0

D4 to D0 indicate data that controls the gain when outputting the L-channel DAC’s output signal to OUTL,

with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.

18:

D5

D4

D3

D2

D1

D0

D4 to D0 indicate data that controls the gain when outputting the R-channel DAC’s output signal to OUTR,

with codes corresponding to the gain levels listed in Table 1-1. Mute mode is set when D5 = 1.

1.6 Test Mode

Test mode is set (and MCLK input is required) when the TEST1 and TEST2 pins are at high level. When in test mode,

the IC internally inputs the ADC’s output directly to the DAC (via an analog loopback). This analog loopback enables

verification of analog circuit operations and the volume settings.

11

Share Link: