TS8308500VGL Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Fabricante
TS8308500VGL Datasheet PDF : 50 Pages
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TS8308500
Timing Diagrams
Figure 2. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at LOW Level
(VIN, VINB)
(CLK, CLKB)
DIGITAL
OUTPUTS
Data Ready
(DR, DRB)
DRRB
X
N-1
1360 ps
1000 ps
TDR = 1320 ps
TA = 250 ps
XN
X
N+1
X
N+2
TC = 1000 ps
TC1 TC2
X
N+3
X
N+4
X
N+5
DATA
N-5
TPD: 4.0 Clock periods
DATA
N-4
DATA
N-3
TDR = 1320 ps
TOD = 1360 ps
DATA DATA
N-2
N-1
DATA
N
DATA
N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
TRDR = 720 ps
1 ns (min)
TD2 = TC2+TOD-TDR
= TC2+40 ps = 540 ps
Figure 3. TS8308500 Timing Diagram (500 Msps Clock Rate), Data Ready Reset, Clock Held at HIGH Level
(VIN, VINB)
XN-1
(CLK, CLKB)
DIGITAL
OUTPUTS
1360 ps
1000 ps
Data Ready
(DR, DRB)
TDR = 1320 ps
DRRB
TA = 250 ps
XN
X
N+1
X
N+2
TC = 1000 ps
TC1 TC2
X
N+3
X
N+4
X
N+5
DATA
N-5
TPD: 4.0 Clock periods
DATA
N-4
DATA
N-3
TDR = 1320 ps
TOD = 1360 ps
DATA
N-2
DATA
N-1
DATA DATA
N
N+1
TD1 = TC1+TDR-TOD
= TC1-40 ps = 460 ps
TRDR = 720 ps
1 ns (min)
TD2 = TC2+TOD-TD
= TC2+40 ps = 540
9
2193A–BDC–04/03
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