TS8308500VGL Ver la hoja de datos (PDF) - Atmel Corporation
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TS8308500VGL Datasheet PDF : 50 Pages
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TS8308500
Table 3. Electrical Specifications (Continued)
Parameter
Test
Symbol Level
Min
Spurious free dynamic range
SFDR
–
–
FS = 500 Msps, FIN = 20 MHz
FS = 500 Msps, FIN = 500 MHz
FS = 500 Msps, FIN = 1000 MHz (-1 dBFS)
FS = 50 Msps, FIN = 25 MHz
Two-tone inter-modulation distortion
–
4
50
–
4
50
–
4
38
–
1
50
IMD
4
–
FIN1 = 199.5 MHz at FS = 500 Msps,
FIN2 = 200.5 MHz at FS = 500 Msps
–
–
-47
Switching Performance and Characteristics – See Figure 2 and Figure 3 on page 9
Maximum clock frequency
Minimum clock frequency
Minimum clock pulse width (high)
FS
–
500
FS
4
10
TC1
4
1.71
Minimum clock pulse width (low)
TC2
4
1.71
Aperture delay
Ta
4
100
Aperture uncertainty
Jitter
4
–
Data output delay
TDO
4
1150
Value
Typ
–
56
53
40
55
–
-52
–
–
2
2
+250
0.4
1360
Max
–
–
–
–
–
–
–
Unit
–
dBc
dBc
dBc
dBc
–
dBc
Note
(2)
(2)
700
50
50
50
400
0.6
1660
Msps
Msps
ns
ns
ps
ps (rms)
ps
(12)
(13)
(2)
(2)(5)
(2)(8)
(9)(10)
Output rise/fall time for data (20%-80%)
Output rise/fall time for data ready (20%-80%)
Data ready output delay
TR/TF
TR/TF
TDR
4
250
350
550
4
250
350
550
4
1110
1320
1620
ps
(9)
ps
(9)
(2)(8)
ps
(9)(10)
Data ready reset delay
TRDR
4
–
720
1000
ps
Data to data ready – Clock low pulse width
(See “Timing Diagrams” on page 9)
(7)(11)
TOD-TDR
4
0
40
80
ps
(12)
Data to data ready output delay (50% duty cycle) at
1 Gsps (See “Timing Diagrams” on page 9)
TD1
4
920
960
1000
ps
(2)(13)
Data pipeline delay
TPD
4
4
clock
cycles
Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA
2. See “Definition of Terms” on page 46
3. Histogram testing based on sampling of a 10 MHz sinewave at 50 Msps
4. Output error amplitude < ±4 lsb around worst code
5. Maximum jitter value obtained for single-ended clock input on the die (chip on board): 200 fs
6. Digital output back termination options depicted in Application Notes
7. At 500 Msps, 50/50 clock duty cycle, TC2 = 2 ns (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate
8. Specified loading conditions for digital outputs:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces
- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input
parasitic capacitance of 1.5 pF including package and ESD protections.)
9. Termination load parasitic capacitance derating values:
- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load
7
2193A–BDC–04/03
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