TS8308500VGL Ver la hoja de datos (PDF) - Atmel Corporation

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Fabricante

TS8308500VGL

ADC 8-bit 500 Msps

Atmel Corporation 

Functional

Description

Block Diagram

Figure 1. Simplified Block Diagram

GAIN

VIN, VINB

Master/Slave Track & Hold Amplifier

Resistor

Chain

Analog

Encoding

Block

4

4

Interpolation

Stages

5

CLK, CLKB

Clock

Buffer

DRRB DR, DRB

GORB

Regeneration

Latches

4

5

Error Correction &

Decode Logic

8

Output Latches &

Buffers

8

DATA, DATAB OR, ORB

Functional

Description

The TS8308500 is an 8-bit 500 Msps ADC based on an advanced high-speed bipolar technol-

ogy featuring a cutoff frequency of 25 GHz.

The TS8308500 includes a front-end master/slave Track and Hold stage (S/H), followed by an

analog encoding stage and interpolation circuitry.

Successive banks of latches are regenerating the analog residues into logical data before

entering an error correction circuitry and a resynchronization stage followed by 75Ω differential

output buffers.

The TS8308500 works in fully differential mode from analog inputs up to digital outputs.

The TS8308500 features a full-power input bandwidth of 1.3 GHz.

Control pin GORB is provided to select either the Gray or Binary data output format.

The gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8308500.

The TS8308500 uses only vertical isolated NPN transistors together with oxide isolated poly-

silicon resistors, which allow enhanced radiation tolerance (no performance drift measured at

150 kRad total dose).

2 TS8308500

2193A–BDC–04/03

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