TRC101 Ver la hoja de datos (PDF) - RF Monolithics, Inc

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Fabricante

TRC101

300-1000 MHz RF Transceiver

RF Monolithics, Inc 

PLL to incrementally change the carrier frequency. The chip can be programmed to automatically

perform an adjustment or may be manually activated by a strobe signal. This function has the advantage

of allowing:

• Cheaper, lower accuracy crystals to be used

• Increased receiver sensitivity by narrowing the receive bandwidth

• Achieving higher data rates

Crystal Oscillator

The TRC101 incorporates an internal crystal oscillator circuit that provides a 10MHz reference, as well as

internal load capacitors. This significantly reduces the component count required. The internal load

capacitance is programmable from 8.5pF to 16pF in 0.5pF steps. This has the advantage of accepting a

wide range of crystals from many different manufacturers having different load capacitance requirements.

Being able to vary the load capacitance also helps with fine tuning the final carrier frequency since the

crystal is the PLL reference for the carrier.

An external clock signal is also provided that may be used to run an external processor. This also has

the advantage of reducing component count by eliminating an additional crystal for the host processor.

The clock frequency is also programmable from eight pre-defined frequencies, each a pre-scaled value of

the 10MHz crystal reference. These values are programmable through the Battery Detect Threshold and

Clock Output Register. The internal clock oscillator may be disabled which also disables the output clock

signal to the host processor. When the oscillator is disabled, the chip provides an additional 196 clock

cycles before releasing the output, which may be used by the host processor to setup any functions

before going to sleep.

Frequency Control (PLL) and Frequency Synthesizer

The PLL synthesizer is the heart of the operating frequency. It is programmable and completely

integrated, providing all functions required to generate the carriers and tunability for each band. The PLL

requires only a single 10MHz crystal reference source. RF stability is controlled by choosing a crystal

with the particular specifications to satisfy the application. This gives the designer the maximum flexibility

in performance.

The PLL is able to perform manual and automatic calibration to compensate for changes in temperature

or operating voltage. When changing band frequencies, re-calibration must be performed. This can be

done by disabling the synthesizer and re-enabling again through the Power Management Register.

Registers common to the PLL are:

• Power Management Register

• Configuration Register

• Frequency Setting Register

• Automatic Frequency Adjust Register

• Transmit Configuration Register

Data Quality Detector (DQD)

The DQD is a unique function of the TRC101. The DQD circuit looks at the prefiltered incoming data and

counts the “spikes” of noise for a predetermined period of time to get an idea of the quality of the link.

This parameter is programmable through the Data Filter Command Register. The DQD count threshold is

programmable from 0 to 7 counts. The higher the count the lower the quality of the data link. This means

the higher the content of noise spikes in the data stream the more difficult it will be to recover clock

information as well as data.

Valid Data Detector

The DDET is an extension of the DQD. When incoming data is detected, it uses the DQD signal, the

Clock Recovery Lock signal, and the Digital RSSI signal to determine if the incoming data is valid. The

DDET looks for valid data transitions at an expected data rate. The desired data rate and the acceptance

criteria for valid data are user programmable through the SPI port. The DDET signal is valid when using

either the internal receive FIFO or an external pin to capture baseband data. The DDET has three modes

of operation: slow, medium, fast. Each mode is dependent on what signals it uses to determine valid data

as well as the number of incoming preamble bits present at the beginning of the packet. The DDET can

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