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TMC1103

Triple Video A/D Converter with Clamps 8-Bit, 50Msps

Fairchild Semiconductor 

TMC1103

PRODUCT SPECIFICATION

Circuit Function

Within the TMC1103 are three 8-bit A/D converters, each

employing two-step architecture to convert an analog input

to a digital output at rates up to 50 Msps. Input signals are

held in integral track/hold stages during the conversion pro-

cess. Operation is pipelined, with one input sample taken and

one output word provided for each CLKX cycle.

Each of the three converters function identically. In the fol-

lowing descriptions ‘X’ refers to a generic input/output or

clock where ‘X’ is equivalent to A, B or C.

The first step in the conversion process is a coarse 4-bit

quantization. This determines the range of the subsequent

fine 4-bit quantization step. To eliminate spurious codes, the

fine 4-bit A/D quantizer output is gray-coded and converted

to binary before it is combined with the coarse result to form

a complete 8-bit result.

Analog Input and Voltage References

Each A/D accepts analog signals in the range RBX to RTX into

digital data. Input signals outside this range produce “satu-

rated” 00h or FFh output codes. The device will not

be damaged by signals within the range AGND to VDDA.

Input range is very flexible and extends from the +5 Volt

power supply to ground. Nominal input range is 2 Volts,

extending from 0.6V to 2.6V. Characterization and

performance is specified over this range. However, the

part will function with a full-scale range from 1.0V to 5.0V.

A smaller input range may simplify analog signal condition-

ing circuitry, at the expense of additional noise sensitivity

and some reduced differential linearity performance.

External voltage reference sources are connected to the RTX

and RBX pins. RBX can be grounded. Within each A/D con-

verter is a reference resistor ladder comprising 255 resistors

that are accessed by the TMC1103 comparators. RTX is con-

nected to the top of the ladder, RBX to the bottom. Gain and

offset errors are directly related to the accuracy and stability

of the applied reference voltages.

Input Clamps

A clamp circuit is connected to the input pin VINX of each of

the three A/D converters. With CLPX LOW, the input pin is

clamped to the voltage at VCLPX. If CLPX is HIGH, the

input pin is high impedance. Clamping adds an offset voltage

to an AC coupled signal to adjust this signal’s amplitude to

the A/D converter input voltage range.

The analog input is corrected through a 0.1mF capacitor to

VINX. The source impedance of the analog source should be

less than 50 Ohms. Current pulses through the capacitor over

several clamp cycles until the voltage across the capacitor

equals the difference between VCLPX and the voltage at the

analog source during the clamping period. When the switch

is open, the voltage on the coupling capacitor is added to the

analog input, producing a a DC offset input signal.

0.1µF

Analog

Input

VINX

A/D Converter

VCLPX

CLPX

Input Clamp Circuit

65-1103-02

Digital Inputs and Outputs

Sampling of the applied input signal occurs on the falling

edge of the CLKX signal (Figure 1). Output data is delayed

by 2 1/2 CLKX cycles and is valid following the rising edge

of CLKX. Previous output data remains valid for tHO (Out-

put Hold Time). New data becomes valid tD (Output Delay

Time) after this rising edge of CLKX.

Whenever the analog input signal is sampled and found to be

at a level beyond the A/D conversion range, the output limits

at 00h or FFh, as appropriate.

Table 1. A/D Output Coding

Input Voltage

RTX + 1 LSB

RTX

RTX - 1 LSB

•••

RBX + 128 LSB

RBX + 127 LSB

•••

RBX + 1 LSB

RBX

RBX - 1 LSB

Note: 1 LSB = (RTX – RBX) / 255

Output

FF

FF

FE

•••

80

7F

•••

01

00

00

The outputs of the TMC1103 are CMOS- and

TTL-compatible, and are capable of driving four low-power

Schottky TTL loads. An Output Enable control, OEX, places

the A/D outputs in a high-impedance state when HIGH.

The outputs are enabled when OEX is LOW.

Power and Ground

The TMC1103 operates from a single +5 Volt power supply.

For optimum performance, an analog ground plane should

be placed under the TMC1103 the AGND and DGND pins

should be connected to the system analog ground plane.

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