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PF28F1602C3TD70

Intel® Advanced+ Boot Block Flash Memory (C3)

Intel 

C3 SCSP Flash Memory

The flash memory is asymmetrically-blocked to enable system integration of code and data storage

in a single device. Each flash block can be erased independently of the others up to 100,000 times.

The flash memory has eight 8-KB parameter blocks located at either the top (denoted by -T suffix)

or the bottom (-B suffix) of the address map, to accommodate different microprocessor protocols

for kernel code location.

The remaining flash memory is grouped into 32-Kword main blocks.

Any individual flash memory block can be locked or unlocked instantly to provide complete

protection for code or data (see Section 5.7, “Flash Erase and Program Timings(1)” on page 34 for

details).

The flash memory contains both a Command User Interface (CUI) and a Write State Machine

(WSM).

• The CUI is the interface between the microcontroller and the internal operation of the flash

memory.

• The internal WSM automatically executes the algorithms and timings necessary for program

and erase operations, including verification, thereby unburdening the microprocessor or

microcontroller. To indicate the status of the WSM, the flash memory status register signifies

block erase or word program completion and status.

Flash program and erase automation enables executing program and erase operations using an

industry-standard two-write command sequence to the CUI.

• Program operations are performed in word increments.

• Erase operations erase all locations within a block simultaneously.

The system software can suspend both program and erase operations to read from any other flash

block. In addition, data can be programmed to another flash block during an erase suspend.

The C3 SCSP memory device offers two low-power savings features to significantly reduce power

consumption:

• Automatic Power Savings (APS) for flash memory. The C3 SCSP memory device

automatically enters APS mode after a read cycle completes from the flash memory.

• Standby mode for flash and SRAM. This mode is initiated when the system deselects the

device by driving F-CE# and S-CS1# or S-CS2 inactive.

To reset the flash memory, lower the F-RP# signal to GND. Setting F-RP# to GND provides CPU

memory reset synchronization and additional protection against bus noise that can occur during

system reset and power-up/power-down sequences.

Datasheet

Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family

Order Number: 252636, Revision: 004

26 Aug 2005

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